Method of decreasing instantaneous current without affecting...

Details Method of decreasing instantaneous current without affecting... Method of decreasing instantaneous current without affecting...

2002-10-21

2004-09-21

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06795954

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is directed to methods for synthesizing balanced clock trees for an integrated circuit design. More specifically, but without limitation thereto, the present invention is directed to distributing a clock signal uniformly over a clock cycle to reduce peak current demand for an array of memory circuits without affecting timing, that is without increasing the worst path delay.
As the number of memories increases in integrated circuit designs, the problem of instantaneous peak current becomes increasingly important. Voltage drop due to the peak current demand from simultaneous switching of a large number of memory devices can result in a malfunction in the operation of the integrated circuit.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power includes receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of the memory cells from the normalized skew calculated for the other clocked cells; and generating as output the recalculated skew for each of the memory cells.
In one embodiment, the function of calculating a first skew for each of the memory cells includes:
constructing a sequence i
0
, i
1
, . . . , i
m
wherein i
0
equals zero and an index i
k+1
=i has a value such that ƒ(M
i
k+1
)<E*(k+1) wherein ƒ(M
i
)=min(t*E+MR(M
i
t
, M
i
), t=0,1, . . . , k), MR(M
i
, M
j
) equals a negative of the length of the edge from vertex V
j
to V
i
, E is a constant greater than zero, m is a positive integer, and k is an integer between 0 and m;
finding a length R(V,MM) of an edge (V,MM) incident to a vertex MM in the third graph;
defining a skew assigned to a vertex V of the third graph on the t-th iteration as SQ(t, V) and setting SQ(0, V) equal to zero for all vertices V of the graph FG;
selecting a vertex V from the third graph having the edges (V
0
, V), (V
1
, V), . . . , (V
k
, V);
defining a function EST(t, V) as the maximum value of the sequence SQ(t, V
i
)+R(V
i
,V), i=0,1, . . . , k; and
calculating a skew for each of the clocked non-memory cells from the function EST(t, V).
In another embodiment, the skew SQ(t+1, V) is calculated substantially from
if
SQ
(
t,V
)<
EST
(
t,V
), then
SQ
(
t
+1
,V
)=
EST
(
t,V
)
otherwise,
SQ
(
t
+1
,V
)=
SQ
(
t,V
)
until SQ(t+1, V) is equal to SQ(t, V) for all vertices V in the third graph.
In another embodiment, the skews SQ
i
t
for the memory cells are calculated substantially according to SQ
i
t
=E*t, t=0,1, . . . , m.
In another embodiment, the length R(V,MM) is the maximum value of the series R(V, M
i
t
)−SQ
i
t
, t=0,1, . . . , k.
In another embodiment, the skews of the clocked non-memory cells are normalized by subtracting a ports skew from each of the skews of the other clocked cells.


REFERENCES:
patent: 6323688 (2001-11-01), Podlesny et al.
patent: 6459313 (2002-10-01), Godbee et al.
patent: 6553370 (2003-04-01), Andreev et al.
patent: 6559701 (2003-05-01), Dillon
patent: 6564211 (2003-05-01), Andreev et al.
patent: 6594797 (2003-07-01), Dudley et al.
patent: 6637014 (2003-10-01), Casavant
patent: 6754120 (2004-06-01), Bellows et al.
Douglas et al., “Power Supply Noise Suppression Via Clock Skew Scheduling,” IEEE, Mar. 20, 2002, pp. 1-6.*
Gupta et al., “Force-Directed Scheduling for Dynamic Power Optimization,” IEEE, Apr. 26, 2002, pp. 1-6.*
Bhupathi et al., “Exploiting Skewed Stated Probabilities For Low Power State Assignment,” IEEE, May 1996, pp. 759-762.*
U.S. patent application Ser. No. 09/891,648, Dillon, filed Jun. 26, 2001.
U.S. patent application Ser. No. 09/679,209, Andreev et al., filed Oct. 4, 2000.
U.S. patent application Ser. No. 09/679,313, Andreev et al., filed Oct. 4, 2000.

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