Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-26
2004-03-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000, C438S628000, C438S553000
Reexamination Certificate
active
06703307
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to implantation after copper (Cu) seed deposition.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. A via is typically a metal plug which extends through an insulative layer. A barrier layer is used to protect the via from metal diffusion and from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, it is characteristic of metals at very high current density and temperatures of 100° C. or more.
Integrated circuit manufacturers have attempted to reduce via resistance as the via size decreases by reducing the thickness of the barrier material. According to one conventional process, plasma vapor deposition (PVD), IC manufacturers deposit a very thin barrier material at the bottom of the via due to non-conformal deposition. The thickness of the barrier material is reduced by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. These advanced deposition processes form highly conformal barrier metal films. However, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration.
FIG. 1
illustrates a schematic cross-sectional view of a portion
100
of an integrated circuit including a copper layer
110
, a copper via
120
, a copper layer
130
, a dielectric layer
150
, and a dielectric layer
160
. Via
120
and copper layer
130
are separated by a barrier layer
140
.
Portion
100
also includes a dielectric layer
142
that is separated from copper layer
130
by an etch stop layer
144
. Dielectric layer
142
can be oxide and etch stop layer
144
can be Silicon Nitride (SiN). Etch stop layer
144
prevents diffusion of copper from copper layer
130
into dielectric layer
142
. Dielectric layer
150
can be separated from copper layer
130
by a barrier layer
152
. Similarly, dielectric layer
160
can be separated by copper layer
110
by a barrier layer
162
. Barrier layers
152
and
162
can be Tantalum Nitride (TaN). Etch stops layers
172
,
174
,
176
, and
178
can also be provided to separate various sections or layers. Etch stop layers
172
,
174
,
176
, and
178
can be Silicon Nitride (SiN).
According to conventional processes, barrier layer
140
can have a cross-sectional thickness of between 7 nm to 25 nm. Barrier layer
140
inhibits diffusion of copper ions from layers into via
120
and from via into dielectric layer
142
. Conventional barrier layers can include Tantalum Nitride (TaN).
FIG. 1
shows a portion formed according to a dual damascene process where copper layer
110
and copper via
120
are deposited in one step or process and are not separated by a barrier.
As discussed above, conventional systems have attempted to reduce the thickness of barrier layer
140
to reduce the resistance associated with via
120
. However, this reduction in thickness can cause electromigration failures.
FIG. 2
illustrates portion
100
described with reference to
FIG. 1
, further having an EM failure or void
145
in copper layer
130
.
FIG. 2
shows a portion formed according to a dual damascene process (as described with reference to
FIG. 1
) where copper layer
110
and copper via
120
are formed in one step or process.
FIG. 3
illustrates portion
100
having an EM failure or void
155
in via
120
due to bulk diffusion from copper layer
110
.
FIG. 3
shows a portion formed according to a dual damascene process (as described with reference to
FIG. 1
) where copper layer
110
and copper via
120
are formed in one step or process.
Electromigration failures have been described by Stanley Wolf, Ph.D. in
Silicon Processing for the VLSI Era
, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264-65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
Thus, there is a need for a barrier that is more resistant to copper diffusion. Further, there is a need for a method of implanting barrier material after copper seed deposition. Even further, there is a need for a method of enhancing barrier properties by providing an interfacial layer proximate a seed layer. Further, there is a need of implanting elements into seed layer.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of fabricating an integrated circuit. This method can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.
Another exemplary embodiment is related to a method of implantation after copper seed deposition in an integrated circuit fabrication process. This method can include providing a first conductive layer over an integrated circuit substrate, providing a conformal layer section at a bottom and sides of a via aperture positioned over the first conductive layer to form a barrier separating the via aperture from the first conductive layer, implanting an element into the conformal layer section to form an implanted layer in the conformal layer section, filling the via aperture with a via material, and providing a second conductive layer over the via material such that the via material electrically connects the first conductive layer to the second conductive layer.
Another exemplary embodiment is related to a method of forming a via in an integrated circuit. This method can include depositing a first conductive layer, depositing an etch stop layer over the first conductive layer, depositing an insulating layer over the etch stop layer, forming an aperture in the insulating layer and the etch stop layer, providing a barrier material at a bottom and sides of the aperture to form a barrier layer, providing a seed layer over the barrier layer, providing an implant into the barrier layer and seed layer to form an implant layer, filling the aperture with a via material, and providing a second conductive layer over the via such that the via electrically connects the first conductive layer and the second conductive layer.
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Besser Paul R.
Buynoski Matthew S.
Lopatin Sergey D.
Advanced Micro Devices , Inc.
Elms Richard
Foley & Lardner
Smith Brad
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