Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-29
2004-04-13
Pert, Evan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S973000
Reexamination Certificate
active
06720632
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a MIS semiconductor device that has a fine structure for realizing high integration of a semiconductor integrated circuit and is capable of operating at high speed and low consumption power and a method for fabricating the same.
In accordance with increase in integration of semiconductor integrated circuits, there is a demand for refinement of MIS semiconductor devices, in particular, MIS transistors, and for this purpose, a MIS transistor with shallow junction is desired.
A method for fabricating a conventional MIS transistor will now be described with reference to
FIGS. 8A through 8E
.
First, as shown in
FIG. 8A
, indium (In) ions, that is, a P-type dopant, are implanted at acceleration energy of 200 keV and a dose of approximately 1×10
12
/cm
2
into a semiconductor substrate
101
of P-type silicon having a principal plane with a <100>-oriented zone axis. After the implantation, annealing is carried out, so as to form a P-type channel diffusion layer
110
a
serving as a channel region in an upper portion of the semiconductor substrate
101
. Subsequently, a gate insulating film
102
with a thickness of approximately 2.2 nm is formed on the semiconductor substrate
101
and a gate electrode
103
of polysilicon with a thickness of approximately 200 nm is formed thereon.
Next, as shown in
FIG. 8B
, with the gate electrode
103
used as a mask, In ions, that is, a P-type dopant, are implanted into the semiconductor substrate
101
at acceleration energy of 100 keV and a dose of approximately 1×10
14
/cm
2
. At this point, a current density for implanting the In ions is approximately 1000 &mgr;A/cm
2
, and the ions are implanted at an angle of approximately 0 through 7 degrees against the normal line of the substrate. Subsequently, arsenic (As) ions, that is, an N-type dopant, are implanted into the semiconductor substrate
101
at acceleration energy of 10 keV and a dose of 5×10
14
/cm
2
. Thereafter, annealing is carried out at a high temperature for a short period of time, so as to form a P-type dopant diffusion layer
104
A and an N-type heavily-doped diffusion layer
105
A with shallow junction in a source/drain region of the semiconductor substrate
101
.
Then, as shown in
FIG. 8C
, a silicon nitride film with a thickness of approximately 50 nm is deposited on the entire surface of the semiconductor substrate
101
at approximately 700° C., and the deposited silicon nitride film is subjected to anisotropic etching, thereby forming a sidewall
106
on the side face of the gate electrode
103
. The sidewall
106
may be formed from a silicon oxide film instead of the silicon nitride film.
Next, as shown in
FIG. 8D
, with the gate electrode
103
and the sidewall
106
used as a mask, As ions, that is, an N-type dopant, are implanted into the semiconductor substrate
101
at acceleration energy of 30 keV and a dose of approximately 3×10
15
/cm
2
, and then annealing is carried out at a high temperature for a short period of time. Thus, an N-type source/drain heavily-doped diffusion layer
107
with deep junction is formed in the source/drain region of the semiconductor substrate
101
, an N-type extension region heavily-doped diffusion layer
105
B with shallower junction than the source/drain heavily-doped diffusion layer
107
is formed on the inside of the source/drain heavily-doped diffusion layer
107
, and a P-type pocket region of heavily-doped diffusion layer
104
B is formed under the extension region heavily-doped diffusion layer
105
B.
Next, as shown in
FIG. 8E
, after a metal film of cobalt or titanium with a thickness of approximately 10 nm and a titanium nitride film with a thickness of approximately 20 nm are successively deposited on the semiconductor substrate
101
by sputtering, annealing is carried out at approximately 550° C. for 10 seconds. Thereafter, the titanium nitride film and an unreacted portion of the metal film are removed by selectively etching them with a mixture of sulfuric acid, hydrogen peroxide and water. Subsequently, annealing is carried out at approximately 800° C. for ten seconds, so as to form a cobalt silicide layer
108
with a thickness of approximately 30 nm in a self-alignment manner in upper portions of the gate electrode
103
and the source/drain heavily-doped diffusion layer
107
.
In this manner, in the conventional method for fabricating a MIS transistor, In ions, that is, heavy ions, are used for the ion implantation for forming the pocket heavily-doped diffusion layer
104
B, so as to realize abrupt dopant profile with shallow junction.
In the conventional method for fabricating a MIS transistor, however, since the heavy ions are used for forming the pocket heavily-doped diffusion layer
104
B, an amorphous layer is formed in the semiconductor substrate
101
when the ions are implanted at a dose exceeding a predetermined dose because the implantation of the heavy ions largely damages the crystal of the semiconductor substrate
101
. Furthermore, through the annealing carried out after the implantation, an EOR (end-of-range) dislocation loop defect layer is formed below the amorphous-crystal interface, and the heavy ions such as In ions are largely segregated in the EOR dislocation loop defect layer.
In particular, in the dopant implantation using heavy ions, the amorphous-crystal interface is formed in a position deeper than the concentration peek of the dopant, and hence, the junction plane obtained after diffusion of the extension heavily-doped diffusion layer
105
B is formed in a position deeper than a designed depth. Furthermore, when the EOR dislocation loop defect layer is formed in the vicinity of the junction plane of the extension region of heavily-doped diffusion layer
105
B, junction leakage is disadvantageously caused.
However, unless heavy ions with a relatively large mass number is used for forming a heavily-doped diffusion layers such as a pocket region and an extension region, it is very difficult to attain shallower junction with currently existing transient enhanced diffusion suppressed. For example, in a CMOS transistor with a design rule of 0.1 &mgr;m, junction depth of approximately 20 nm through 30 nm is required of the extension heavily-doped diffusion layer
105
B. In this case, the As ions are probably moved by as large as approximately several tens nm owing to the transient enhanced diffusion caused by the annealing carried out at a low temperature for forming the sidewall
106
. Accordingly, when a MIS transistor is further refined, even when the ion implantation is carried out at small acceleration energy, the junction depth of the extension heavily-doped diffusion layer
105
B is unavoidably increased to exceed a target value through the subsequent annealing.
The transient enhanced diffusion is a phenomenon that excess point defects and an implanted dopant are diffused through the interaction, resulting in diffusing the dopant more largely than the diffusion coefficient in the thermal equilibrium state.
SUMMARY OF THE INVENTION
The present invention was devised for overcoming the aforementioned conventional problems, and an object is suppressing occurrence of dislocation loop defects derived from heavy ions while using the heavy ions indispensable for attaining shallow junction in forming heavily-doped diffusion layers serving as an extension region and a pocket region.
In order to achieve the object, in a MIS semiconductor device and a fabrication method for the same according to the invention, a semiconductor substrate capable of suppressing the formation of a defect layer is used, or heavy ions are implanted so as to reduce implantation damage caused during the implantation and so as to minimally form a defect layer in a semiconductor substrate itself.
Specifically, the first semiconductor device of this invention comprises a heavily-doped diffusion layer formed, by using a dopant ion having a relatively large mass number, in an epitaxial region of silicon included in at least an upper
Nixon & Peabody LLP
Pert Evan
Sarkar Asok Kumar
Studebaker Donald R.
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