Test vehicle with zig-zag structures

Details Test vehicle with zig-zag structures Test vehicle with zig-zag structures

2002-07-24

2004-09-07

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S774000

Reexamination Certificate

active

06787800

ABSTRACT:

FIELD OF INVENTION
This invention relates to methods for measuring and evaluating the process and design related statistical variations of an integrated circuit manufacturing process in order to determine their sources and their effects on the yield and performance of the product.
BACKGROUND
Defects (e. g. particles) can cause electrically measurable faults (killer defects), which are dependent on the chip layout as well as the layer and location of the defects. These faults are responsible for manufacturing related malfunction of chips. So, a layer and fault sensitive defect density is important for yield enhancement and to control quality of process steps and product chips, as discussed in Staper, C. H., Rosner, R. J., “Integrated Circuit Yield Management and Yield Analysis: Development and Implementation,” IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995, which is incorporated by reference herein. Test structures are used to detect faults and to identify and localize defects.
A chain of vias and/or contacts are usually used to observe the integrity of Inter Layer Dielectric (ILD) layers.
FIGS. 1A-1C
show a typical via chain, of a type described in Ipri, A. C., Sarace, J. C., “Integrated Circuit Process and Design Rule Evaluation Techniques,” RCA Review, pp. 323-350, Volume 38, Number 3, September 1977, and Buehler, M. G., “Microelectronic Test Chips for VLSI Electronics,” VLSI Electronics Microstructure Science, pp. 529-576, Vol 9, Chapter 9, Academic Press, 1983, both of which are incorporated by reference herein.
FIG. 1A
shows the total layout used to check chain continuity/resistance, including the bottom polysilicon (P-Si) layer
114
, and the metallization (M
1
) layer
116
, with contacts
118
for the vias between the layers.
FIG. 1B
shows the bottom P-Si pattern.
FIG. 1C
shows the top M
1
pattern.
FIG. 3A
shows facing line ends in a dense environment. Layer
314
may be a poly-silicon (P-Si) layer. Layer
316
may be a metallization layer. Vias
314
in the ILD
311
connect layers
314
, and
316
.
FIG. 3B
shows facing line ends in an isolated environment, including P-Si layer
324
, metallization layer
326
and vias
328
. If a defect occurs in the ILD layer
321
, the via
328
between the upper and lower conducting layers
326
and
324
, respectively, will fail and result in a measurable short circuit (not shown).
FIG. 3C
shows facing line ends in an isolated environment with top metal misalignment, including P-Si layer
334
, metallization layer
336
and ILD
331
with vias
338
. Beside defect dependent open vias, misalignment between the via
338
and conducting layers
336
can occur in product chips during the manufacturing steps. This can also cause short circuits
339
within the metal layer
336
as shown in FIG.
3
C. In addition to that, the space between metal lines will vary due to the metal density in deep submicron technologies using Deep Ultra Violet (DUV) (short light wave length) and beyond lithography steps.
Furthermore, so-called line end shortening effects as illustrated in
FIG. 4
are becoming an important yield-limiting factor.
FIG. 4
shows line end shortening effect and its impact on possible open circuit faults in the via/contact layer as well as its impact on possible short circuit faults in the metal layer. Only the upper metal layer and contacts are shown in
FIG. 4
, for ease of viewing. The metal patterns are indicated by
402
a
,
402
b
,
404
a
,
404
b
,
406
a
,
406
b
,
408
a
,
408
b
,
411
a
, and
411
b
. Contacts are indicated by
401
a
,
401
b
,
403
a
,
403
b
,
405
a
,
405
b
,
407
a
,
407
b
,
409
a
,
409
b
,
410
a
and
410
b
. Metal patterns
406
a
and
406
b
are nominally sized and provide complete coverage over respective contacts
405
a
and
405
b
, reflected in low resistance. Metal patterns
402
a
,
402
b
,
404
a
and
404
b
are shortened, resulting in reduced overlap with respective contacts
401
a
,
401
b
,
403
a
and
403
b
. This increases resistance, and may result in open circuits, for example, in the case of contacts
401
a
and
401
b
. Metal patterns
408
a
,
408
b
,
411
a
and
411
b
have respective extensions
409
a
,
409
b
,
412
a
and
412
b
. If excessively long, the extensions may result in a short circuit, for example in the case of extensions
412
a
and
412
b.
FIG. 2
shows the tradeoff between the yield loss of via open circuit faults (curve
201
) and the yield loss of metal short circuit faults (curve
202
). The X-axis represents the via border overlap (in the case of open circuit faults) or line extension (in the case of short circuit faults). That is, the X-axis shows the extension of the metal or poly layer over the contact or via, respectively. The sum of these two curves may be approximated by a downward-facing parabola (not shown). To ensure optimal yield of product chips within such a manufacturing environment, the yield loss of metal short circuit faults
202
has to be balanced against yield loss of via open circuit faults
201
as shown in FIG.
2
. The optimal value is that at which the total yield loss is minimized (or total yield is maximized).
Two parallel via chains as described in Doong, K., Cheng, J., Hsu, C., “Design and Simulation of Addressable Fault Site Test Structure for IC Process Control Monitor,” International Symposium on Semiconductor Manufacturing, 1999, which is incorporated herein by reference. Multiple interwoven via chains which allow for the detection of open and short circuits are described in Hess, C., Weiland, L. H., “Influence of Short Circuits on Data of Contact & Via Open Circuits Determined by a Novel Weave Test Structure,” IEEE Transactions on Semiconductor Manufacturing, pp. 27-34, Vol. 9, No. 1, 1996, which is incorporated herein by reference.
Improved test vehicles are desired.
SUMMARY OF THE INVENTION
The present invention is a test vehicle having a plurality of zig-zag structures.


REFERENCES:
patent: 6475871 (2002-11-01), Stine et al.
Doong, K. et al., Design and Slmulation of Addressable Failure Site Test Structure for IC Process Control Monitor, pp. 219-222 Worldwise Semiconductor Manufacturing Corp. Shinchu, Taiwan.*
Doong, K. et al., Design and Simulation of Addressable Failure Site Test Structure for IC Process Control Monitor, pp. 219-222, Worldwide Semiconductor Manufacturing Corp. Shinchu, Taiwan; Microelectronics Laboratory, Semiconductor Technology & Application Research (STAR) Group, Dept. of Electrical Engineering, National Tsing-Hua University, R.O.C..
Hess and Weiland, Influence of Short Circuits on Data of Contact and Via Open Circuits Determined by a Novel Weave Test Structure, pp. 27-34, IEEE Transactions on Semiconductor Manufacturing, vol. 9 No. 1, Feb. 1996.
Stapper and Rosner, Integrated Circuit Yield Management and Yield Analysis: Development and Implementation, pp. 95-102, IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2, May 1995.

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