Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-11-13
2004-04-06
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S283000
Reexamination Certificate
active
06716684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a structure and a method for constructing a triple-gate transistor device, particularly a triple-gate transistor.
2. Description of the Related Art
Multiple-gate transistors have a number of different uses. However, construction of vertical multiple-gate devices has always been somewhat difficult, given alignment problems between the gates used in the device.
FIG. 1
shows a cross-sectional view of a double-gate device formed on a silicon substrate
10
having a top gate
12
and a bottom gate
14
formed in a buried oxide layer
16
. Construction of gates
12
and
14
in this stacked type of device leads to alignment problems between the vertically separated top and bottom gates
12
and
14
, respectively. In addition, care must be taken to provide ample connectivity for gate
14
.
Simplification and self-alignment in semiconductor processing methods is constantly advantageous. Hence a method which provides a simplified method for forming a multiple-gate device would be advantageous.
SUMMARY OF THE INVENTION
The invention, roughly described, comprises a self-aligned transistor. The transistor includes a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.
In a further embodiment, the invention comprises a method for manufacturing a transistor device. The method for manufacturing includes the steps of: providing a substrate having a buried oxide region; depositing a first nitride mask layer having a pattern overlying a silicon region; forming a trench in said substrate with a depth to said buried oxide; depositing a conformal oxide in said trench; forming vias in said conformal oxide adjacent to said silicon region and removing a portion of said first nitride mask to expose a portion of said silicon region; depositing polysilicon in said vias and on said portion of said silicon region; and implanting an impurity into exposed portions of polysilicon in said trench and of said silicon-on-insulator substrate underlying said second nitride layer.
REFERENCES:
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5583059 (1996-12-01), Burghartz
patent: 6225147 (2001-05-01), Noble et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
Buynoski Matthew
Krivokapic Zoran
Advanced Micro Devices , Inc.
Fliesler & Meyer LLP
Loke Steven
Owens Douglas W.
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