Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-02
2004-09-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06799305
ABSTRACT:
BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to methods for laying out electronic circuits and programs thereof wherein the maximum wire length ensuring a normal operation in a unit of each wire is calculated when a layout of an electronic circuit is designed.
(ii) Description of the Related Art
Conventionally, in wiring layouts of electronic circuits, a problem of conversion of digital logic circuit information into geometric configuration information has been regarded as most important. Taking in various techniques, laying out at very high density and with efficiency has become possible. However, because any distinct index from the viewpoint of signal reliability has not been given, problems that a completed circuit does not operate or is instable have occurred particularly in highly integrated circuits such as LSIs (Large Scale Integrations).
For developing circuits that operate stably, a countermeasure by experimental knowledge is required. For example, for taking matching in impedance between circuit elements, or for satisfying a delay restriction of a path, circuit elements may be disposed by a manual work in designing a layout, and/or a logic connection relation may be altered a manual work. As a result, there is a wide difference between a less experienced engineer and a well experienced engineer. However, even if well experienced, the engineer can not always design a circuit that operates normally, where there is indeterminacy.
Methods to solve such problems in designing stage have been proposed. In Japanese Patent Application Laid-open No. 2000-163460, a wiring imaginary capacitance of a wire is introduced out in designing a layout, and a permissible current quantity of the wire and a wire width that allows the permissible current to flow are calculated. The layout processing is performed on the basis of those permissible current quantity and wire width.
However, according to the prior art disclosed in the Japanese Patent Application Laid-open No. 2000-163460, the wiring capacitance which is a physical quantity as a concentrated (lumped) constant, is used for evaluation of signal reliability. It is an improper index for a high-speed digital circuit wherein characteristics as a transfer line of distributed constant series becomes remarkable. Besides, there is also inconvenience that a delay library is necessary in advance.
SUMMARY OF THE INVENTION
The present invention has been made by taking the above circumstances into consideration, and its object is to provide a method for laying out electronic circuits and a program thereof, capable of defining restriction of wire length from the viewpoint of signal reliability and ensuring signal reliability in designing a layout.
According to one feature of the present invention, there is provided a method for laying out an electronic circuit, which method comprises the first step of inputting a net list of an electronic circuit as a design target, and setting a plan of an layout from the net list; the second step of inputting a structure of each wire and an electrical characteristic of a circuit element connected to the wire, on the basis of the net list; the third step of inputting a condition for a circuit element connected to a terminal end of the wire to operate normally; the fourth step of calculating a maximum wire length that ensure to operate normally, using parameters input in the second step and the third step; the fifth step of comparing a wire length based on the plan of the layout and the maximum wire length; and the sixth step of again setting a plan of an layout in case that the wire length based on the plan of the layout is longer than the maximum wire length as a result of comparing in said fifth step.
The second step of the method of the present invention preferably inputs a dielectric constant of a substrate, a path impedance of the wire, and impedances of circuit elements connected to both ends of the wire.
Further, the third step of the method of the present invention preferably inputs an upper limit value of a signal delay time and a threshold of a voltage in which circuit elements connected to both end of the wire can operate normally.
Moreover, the fourth step of the method of the present invention preferably calculates the propagation velocity on the basis of a dielectric constant of a substrate, preferably calculates a reflection period and a reflection frequency on the basis of the propagation velocity, preferably calculates ratios of reflection (reflectances) of circuit elements connected to both ends of the wire, on the basis of a path impedance of the wire and impedances of the circuit elements, respectively, preferably substitutes the propagation velocity, the reflection period, the reflection frequency, the ratios of reflection, and the condition input in the third step for a relational expression of a voltage change in relation to time of a signal propagating in the wire, and calculates the maximum wire length on the basis of the relational expression.
According to the other aspect of the present invention, there is provided a program causing a computer to execute a procedure of setting a plan of an layout from a net list of an electronic circuit as a design target; a procedure of calculating a maximum wire length ensured to operate normally,. from each wire structure, an electrical characteristic of a circuit element connected to the wire, and a condition for a circuit element connected to a terminal end of the wire to operate normally, input on the basis of the net list; a procedure of comparing a wire length based on the plan of the layout and the maximum wire length; and a procedure of again setting a plan of an layout in case that the wire length is longer than the maximum wire length from the comparison result.
Moreover, the procedure of calculating a maximum wire length of the program of the present invention preferably includes a calculation of a propagation velocity on the basis of a dielectric constant of a substrate, a calculation of a reflection period and a reflection frequency on the basis of the propagation velocity, and a calculation of ratios of reflection of circuit elements connected to both ends of the wire, on the basis of a path impedance of the wire and impedances of the circuit elements, respectively.
Furthermore, the procedure of calculating a maximum wire length of the program of the present invention preferably includes substitutions of said propagation velocity, the reflection period, the reflection frequency, the ratios of reflection, and the normally operating conditions of the circuit element for a relational expression of a voltage change in relation to time of a signal propagating in the wire.
REFERENCES:
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6651237 (2003-11-01), Cooke et al.
patent: 2000-163460 (2000-06-01), None
Do Thuan
NEC Corporation
Sughrue & Mion, PLLC
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