Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2003-04-30
2004-09-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S701000, C257S758000, C257S774000, C257S773000
Reexamination Certificate
active
06787928
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a structure of IC pad and its forming method, in particular to a structure and method that are adapted to form a pad of integrated circuit of high frequency and low noise; not only the noise from the semiconductor substrate be separated effectively and the value of equivalent electric capacitance of the pad be lowered, but also the bonding adherence be further enhanced.
BACKGROUND OF THE INVENTION
Recently, since the requirement of transceiver of low power and low cost is steadily on the increase, so the technology of mainstream IC competitively concentrates on how to realize further more functions of radio frequency on one single chip. Except making integrated circuit be able to arrange on the package substrate, the external circuit connected by the external legs of package substrate must be electrically connected to the integrated circuit. So, when packaging the integrated circuit, the technology of pad has become an important factor that influences the yield and quality of a product. This pad adapted for providing electric connection between the integrated circuit and the external circuit is usually arranged in the metal zone around the IC die. When the pad is formed, the metal connecting wire must contact with the pad accurately and connect to the external legs of the IC packaging substrate. Because of the limitation of the prior arts and the characteristics of metal connecting wire and pad, the area of pad is sometimes too large to occupy too much area of chip. Furthermore, during high frequency, the performance of the integrated circuit is influenced because the equivalent electric capacitance is too large.
Additionally, because of the market growth of communication IC recently, the operational frequency of integrated circuit is also growing in indexing type. The low noise and low loss of high frequency signal are always the pursuing goals for communication IC.
In 1987, the U.S. Pat. No. 4,636,832 “Semiconductor device with an improved bonding section” proposed a design method of the pad of integrated circuit. Please refer to
FIG. 1
, which is a cross-sectional diagram of the IC device disclosed in the U.S. Pat. No. 4,636,832. The characteristic of this prior art is that the semiconductor element
10
is arranged below the pad
15
. Although it may reduce the area of layout, this kind of pad can not be adapted to high frequency circuit with low noise because the noise coming from the semiconductor substrate
20
will directly influence the signal of high frequency when it passes through the pad.
To overcome the tensile and tension of bonding, the U.S. Pat. No. 5,248,903 “Composite pads for semiconductor devices” proposed a kind of pad. Please refer to
FIG. 2
, which is the cross-sectional diagram of the IC device disclosed in the U.S. Pat. No. 5,248,903. Wherein, the pad
30
has at least two layers of electric-conduction layer
30
a
and
30
c
and a connection layer
30
b
. But, this kind of pad is not adapted for the signals of high frequency and low noise because the noise of semiconductor substrate
35
will directly influence the quality of signal.
The U.S. Pat. No. 5,502,337 “Semiconductor device structure including multiple interconnection layers with interlayer insulating films” proposed a different designing method for pad. Please refer to
FIG. 3
, which is a cross-sectional diagram for the IC device disclosed in the U.S. Pat. No. 5,502,337, which arranges the connection layer
40
a
in the pad
40
around the bonding zone
45
. When the integrated circuit is manufactured, a bonding zone of arc shape will be formed on the pad
40
to thereby enhance the bonding adherence. However, the technology of current integrated circuit has stepped into the levels of sub micrometer or deep sub micrometer, and CMP (Chemical-Mechanical Polish) is already a standard procedure for current semiconductor process. So, this kind of prior art no longer generates original effectiveness in current semiconductor process, besides this technique has the same drawback as that of previous techniques; i.e., it can not separate the noise coming from the semiconductor substrate
50
.
From above discussion, we know that the prior arts described there are unable to propose an effective solution that aims for the high frequency, low noise and bonding adherence. Therefore, the emphasis of the invention is to provide a pad structure adapted for a integrated circuit of high frequency and low noise to lower down the equivalent electric capacitance and enhance the bonding adherence, such that it can prevent the entire pad from being drawn out of the semiconductor chip by the tension generated in the bonding procedure.
SUMMARY OF THE INVENTION
The main objective of the present invention is to provide a structure of IC pad and its forming method, which are adapted for the structure of the pad of an integrated circuit of high frequency and low noise, such that the effective area of the pad may be reduced effectively to thereby reduce its value of equivalent electric capacitance.
The second objective of the present invention is to provide a structure of IC pad and its forming method effectively separate the noise coming from the semiconductor substrate.
The further objective of the present invention is to provide a structure of IC pad and its forming method effectively enhance the bonding adherence, such that it prevent the entire pad from being drawn out of the semiconductor chip by the tension generated in the bonding procedure.
To achieve above objectives, the invention provides an IC pad structure arranged in an insulation layer comprises a lower electric-conduction layer, a compound layer structure and a pad layer.
The lower electric-conduction layer is arranged in the insulation layer and is connected to an electric potential.
The compound layer structure arranged on the insulation layer comprises at least one electric-conduction layer and at least one electric-conduction connecting layer, each of the electric-conduction layer are connected to each other.
The pad layer is arranged on the compound layer structure.
To achieve above objectives, the invention further presents method for forming IC pad structure, comprising the following steps of:
Step (a): providing a substrate arranged with an insulation layer.
Step (b): forming a lower electric-conduction layer which prepared connect to an electric potential.
Step (c): forming a compound layer structure composed by inter-overlapping or connect at least one electric-conduction layer and at least one electric-conduction connecting layer on the insulation layer.
Step (d): forming a pad layer on the compound layer structure, of which area is larger than that of the electric-conduction layer of the compound layer structure.
REFERENCES:
patent: 5284797 (1994-02-01), Heim
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 5923088 (1999-07-01), Shiue et al.
patent: 5986343 (1999-11-01), Chittipeddi et al.
patent: 6163074 (2000-12-01), Lee et al.
patent: 6313537 (2001-11-01), Lee et al.
patent: 6465337 (2002-10-01), Lee et al.
patent: 2001/0000928 (2001-05-01), Lee et al.
Flynn Nathan J.
Greene Pershelle
Realtek Semiconductor Corp.
Troxell Law Office PLLC
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