Output buffer circuit

Details Output buffer circuit Output buffer circuit

2003-04-18

2004-09-28

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S035000, C326S112000

Reexamination Certificate

active

06798247

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2002-163758, filed on Jun. 5, 2002, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit including a driving capability control circuit which performs control to change driving capability of an output buffer during its operation.
2. Description of the Related Art
With a recent remarkable increase in the operation speed of an integrated circuit, a high-speed output buffer has also been demanded of its output buffer. To meet this demand, improvements in the driving capability of the output buffer are made, but the improvements caused the problem of noises such as overshoot, undershoot, and ringing.
Hence, the output buffer has been faced the contradictory demands, that is, an improvement in driving force and a reduction in noise at the same time.
One of solutions thereto is to change the driving capability of the output buffer during its operation. The increase in speed demanded of the output buffer of a digital circuit means that the signal reaches earlier to the logical threshold of the next stage, and therefore high driving capability is required for the output buffer from the start of state transition to its arrival at the logical threshold level of the next stage.
On the other hand, noise tends to occur after the output signal reaches the logical threshold of the next stage, and especially when the driving capability is high, noise markedly occurs. To reduce the noise, it is effective to reduce the driving capability of the output buffer after the signal reaches the logical threshold of the next stage.
FIG. 6
shows the circuit configuration of a related complementary MIS output buffer control circuit. An input
101
is connected to a main buffer
103
of an output buffer via a subbuffer
102
. The main buffer
103
is connected to an output terminal
104
and drives a load capacitance
105
. A driving assistant buffer
106
including a P-channel MISFET (hereinafter referred to as a P-MIS)
106
1
for enhancing rise driving force and an N-channel MISFET (hereinafter referred to as an N-MIS)
106
2
for enhancing fall driving force is connected in parallel with the main buffer
103
.
A two-input NAND
108
is connected to a gate terminal of the P-MIS
106
1
, and a two-input NOR
109
is connected to a gate terminal of the N-MIS
106
2
. Both inputs of the NAND
108
and the NOR
109
are the input
101
and an inverted output by an inverter
107
of the output terminal
104
. Namely, on/off control of the driving assistant buffer
106
is performed by the input
101
and a feedback from the output terminal
104
.
Incidentally, a parasitic inductance
110
such as a pin, a bonding wire, or the like of an integrated circuit package exists between the output terminal
104
and the load capacitance
105
.
Now, the operation of the driving assistant buffer
106
during an output transition is explained. First, when the input
101
is “H” and both its input and output are stable, the output terminal
104
is also “H”, and hence an output of the inverter
107
is “L”. Accordingly, an output of the NAND
108
is “H”, and an output of the NOR
109
is “L”, whereby both the P-MIS
106
1
and the N-MIS
106
2
are turned off, that is, the driving assistant buffer
106
does not function.
When the input
101
changes from “H” to “L”, the output terminal
104
also starts to change from “H” to “L”, but there exists an output delay time which depends on the magnitude of the load capacitance
105
. Accordingly, the output of the inverter
107
remains “H” immediately after the change of the input
101
from “H” to “L”. Therefore, both inputs of the NOR
109
are “L” and the output thereof is “H”, so that the N-MIS
106
2
is turned on.
On the other hand, since the input
101
becomes “L”, the output of the NAND
108
remains “H”, and the P-MIS
106
1
remains off.
Namely, during this period, the driving assistant buffer
106
enhances the driving force which makes an output of the main buffer
103
to fall by turning only the N-MIS
106
2
on.
Thereafter, when the level of the output terminal
104
exceeds a logical threshold of the inverter
107
, the output of the inverter
107
becomes “H”, and the output of the NOR
109
becomes “L”, whereby the N-MIS
106
2
is turned off. Thus, the operation of the driving assistant buffer
106
is completed. In other words, the driving assistant buffer
106
functions from when the level of the output terminal
104
started to change until it exceeds the logical threshold of the inverter
107
.
FIG. 7
is a operation waveform diagram of the output buffer circuit. At early stages of the fall of an output waveform, the output waveform sharply falls since both the main buffer
103
and the driving assistant buffer
106
operate, but when the output level exceeds the logical threshold of the inverter
107
, the driving assistant buffer
106
stops its operation, and hence the output change becomes gradual.
Incidentally, when the input
101
changes from “L” to “H”, the output of the NAND
108
stays “L” until the level of the output terminal
104
exceeds the logical threshold of the inverter
107
, and the P-MIS
106
1
is turned on to thereby increase the speed of output change immediately after rise (not shown in FIG.
7
).
Thus, in the circuit in
FIG. 6
, both the inverter
107
and the NOR
109
or the NAND
108
perform the operation of controlling the driving force of the output buffer in such a manner that the driving force is increased immediately after the output transition and reduced from the middle of the transition.
The related complementary MIS output buffer control circuit, however, has a problem that internal oscillation tends to occur when the driving force is reduced in the middle of the transition. This is because the rate of current change per unit time increases due to a sharp change in driving force and counter electromotive force generated by the product of the current change rate and the parasitic inductance
110
increases to thereby return the output change in the opposite direction.
The output considered as temporarily exceeding the logical threshold of the inverter
107
by this counter electromotive force is considered again as having the logical threshold or less, and the driving assistant buffer
106
is turned on again. Then, the counter electromotive force which acts in the opposite direction to the previous direction is generated, and this time it acts so as to turn off the driving assistant buffer
106
. The repetition of this operation causes oscillation, and
FIG. 8
shows an example of its simulation.
A factor which causes the sharp change in driving force is a high gain of the driving force control circuit including the inverter
107
and the NAND
108
or the NOR
109
which controls the driving assistant buffer
106
.
FIG. 9
shows a portion including the inverter
107
and the NOR
109
extracted from the driving force control circuit with a case when the output terminal
104
changes from “H” to “L” as an example, and herein the NOR
109
is represented by a MISFET.
In
FIG. 9
, immediately after the change of the input
101
from “H” to “L”, the output terminal
104
still remains “H”, and a NOR input
109
1
which is an inverted output of the inverter
107
remains “L”. Accordingly, a NOR output
109
2
is “H”.
Thereafter, when the output terminal
104
changes to “L”, the NOR input
109
1
changes to “H”. Then, a P-MIS
109
3
changes its state from ON to OFF, and an N-MIS
109
4
changes its state from OFF to ON, whereby the NOR output
109
2
becomes “L”. At this time, changes in the states of the P-MIS
109
3
and the N-MIS
109
4
simultaneously occur, and hence the change of the NOR output
109
2
from “L” to “H” is sharp.
FIG. 10
shows the voltage transition of the NOR output
109
2
with respect to the voltage transition of the output t

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