Semiconductor device having a logic transistor therein

Details Semiconductor device having a logic transistor therein Semiconductor device having a logic transistor therein

2001-08-17

2004-01-06

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000, C257S306000, C257S401000, C438S183000, C438S740000, C438S970000

Reexamination Certificate

active

06674111

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device including a DRAM (Dynamic Random Access Memory) memory cell and a manufacturing method of the same. More particularly, the present invention relates to a semiconductor device incorporating a logic transistor therein, and a manufacturing method of the same.
Recent progress in semiconductor fine processing technology has enabled semiconductor elements integrated at 1-giga level to be formed on a single semiconductor LSI (Large-Scale Integration). Thus, a system that is conventionally formed from several semiconductor LSIs of separate chips is about to be formed on a single chip (system on silicon). The current main technology for implementing this system is an embedded DRAM (e-DRAM), i.e., integration of a high-speed logic LSI with a DRAM, a mass-storage general-purpose memory.
A memory cell in the DRAM is formed from a capacitor having a capacity insulating film, and a MIS (Metal Insulator Semiconductor) transistor for charging and discharging the capacitor. A thermal processing at about 800° C. (formation of a thermal oxide film) is required to form the capacity insulating film. Technology for forming the capacity insulating film at a reduced temperature by using a highly dielectric material such as a tantalum oxide film (a lower-temperature process) is under study, but has not reached a practical level. On the other hand, in the logic LSI requiring a high-speed operation, reduction in the gate length of the MIS transistor is an essential requirement. Therefore, a lower-temperature process is required in order to suppress impurity diffusion and thus the short-channel effect. In order to integrate the DRAM and the logic LSI on the same chip, the process must be conducted successively while recognizing the difference in need for the lower-temperature process between the DRAM and the logic LSI.
In this case, in the DRAM having a trench-type memory cell structure, i.e., a structure in which the cell plate electrode and the capacity insulating film of the capacitor are disposed in a trench, the capacitor can be formed before formation of the MIS transistor. Accordingly, even if the respective MIS transistors of the DRAM and the logic LSI are formed in a common process after formation of the capacitor, problems resulting from the difference in need for a reduced process temperature between the DRAM and the logic LSI can be easily avoided. Thus, the trench-type memory cell structure is said to be suitable for the e-DRAM. However, the step for forming the capacitor is complicated, and also reduction in the memory cell size is significantly restricted. Therefore, a stacked memory cell structure employed in many DRAMs, i.e., a structure in which the capacitor is provided above the MIS transistor, has been regarded as appropriate.
In the stacked memory cell structure, the following process has been proposed and practiced in order to avoid the problems due to the thermal processing: first, an MIS transistor of the DRAM memory section and a capacitor provided thereon with an interlayer insulating film therebetween are formed. In this step, a gate electrode and an LDD (Lightly Doped Drain) region of the MIS transistor of the logic section are formed, but high-concentration source/drain regions are not formed yet. Thereafter, the interlayer insulating film covering also the logic section is removed, and the source/drain regions of the MIS transistor of the logic section and the like are formed.
FIGS. 9A
to
11
B are cross-sectional views illustrating an example of a conventional method for manufacturing an e-DRAM semiconductor device using such a process. More specifically,
FIGS. 9A
to
9
C illustrate from the beginning of the manufacturing process of the semiconductor device to the step of forming a storage node electrode in a DRAM memory section.
FIGS. 10A and 10B
illustrate from the step of forming a capacitor of the DRAM memory section to the step of removing a first interlayer insulating film and forming a sidewall.
FIGS. 11A and 11B
illustrate from the step of forming a second interlayer insulating film to the step of forming a wiring layer.
First, in the step of
FIG. 9A
, an element-isolation insulating film
501
surrounding active regions of a DRAM memory section and a logic section is formed at a silicon substrate
500
. Then, a silicon oxide film and a polysilicon film are sequentially deposited on the substrate. Thereafter, these films are patterned to form a gate insulating film
502
and a gate electrode
503
of each MIS transistor of the DRAM memory section and the logic section. At this time, a gate line
504
connected to the gate electrode
503
of the logic section and a gate line
505
connected to the gate electrode
503
of the DRAM memory section are formed on the element-isolation insulating film
501
. Then, impurities are introduced into the active regions of the logic section and the DRAM memory section by ion implantation or the like, thereby forming LDD regions
507
of the MIS transistor of the logic section as well as source/drain regions
508
of the MIS transistor (memory cell transistor) of the DRAM memory section.
In the step of
FIG. 9B
, a thin silicon nitride film
509
is deposited on the substrate so as to cover the gate electrodes
503
and the gate lines
504
,
505
. Then, a first interlayer insulating film
510
of a silicon oxide film is deposited on the substrate. After planarizing the first interlayer insulating film
510
, contact holes are formed in the DRAM memory section so as to extend through the first interlayer insulating film
510
and the silicon nitride film
509
to the source/drain regions
508
and the gate line
505
, respectively. At this time, no contact hole is formed in the logic section. Then, each contact hole is filled with a conductor film (e.g., a polysilicon film or a tungsten film), thereby forming a conductor plug
511
a
(part of a storage node) connected to the source of the source/drain regions
508
of the MIS transistor of the DRAM memory section, a conductor plug
511
b
(bit-line contact) connected to the drain of the source/drain regions
508
, and a conductor plug
511
c
(word-line contact) connected to the gate line
505
. Note that the conductor plugs
511
b
,
511
c
are not necessarily formed in the cross section of FIG.
9
B and
FIGS. 9C
to
11
B described below, but are shown as being present in this cross section for better understanding.
Then, in the step of
FIG. 9C
, a thin silicon nitride film
512
is formed on the substrate so as to cover the first interlayer insulating film
510
and the conductor plugs
511
a
to
511
c
. Thereafter, a silicon oxide film
513
is deposited on the substrate. The silicon oxide film
513
and the silicon nitride film
512
are selectively removed to form an opening such that the conductor plug
511
a
on the source of the source/drain regions
508
of the DRAM memory section is exposed at the bottom of the opening. Then, a polysilicon film and a photoresist film are formed on the substrate, and the top surface of the substrate is planarized by using an etch-back method. Thus, a bottomed cylindrical storage node electrode
514
of the polysilicon film as well as a photoresist portion
550
that fills a recess formed by the storage node electrode
514
are formed in the opening.
In the step of
FIG. 10A
, the photoresist portion
550
is removed by ashing or the like, and then the silicon oxide film
513
is selectively removed using hydrofluoric acid or the like. Then, a very thin silicon nitride film is deposited on the substrate, and the surface of the silicon nitride film thus deposited is oxidized to form a capacity insulating film
515
on the storage node electrode
514
. Note that, although not shown in
FIG. 10A
, a stacked layer of the silicon nitride film and the silicon oxide film is formed also on the silicon nitride film
512
. Then, a polysilicon film is deposited on the substrate, and a photoresist film
551
is formed so as to cover the DRAM mem

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