Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1998-03-04

2003-11-25

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S392000, C257S393000, C257S401000

Reexamination Certificate

active

06653693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device of a low electric power consumption type.
2. Description of the Prior Art
FIG. 1
is a circuit diagram showing the configuration of a circuit capable of performing under a low electric voltage as a semiconductor integrated circuit device that will be used for explanation of preferred embodiments according to the present invention and following conventional examples. The diagram of this circuit capable of performing under the low voltage shown in
FIG. 1
was also disclosed in the patent document of Japanese patent laid open publication number JP-A-7/212218 as a conventional semiconductor integrated circuit device.
The circuit capable of performing under a low electrical voltage as a semiconductor integrated circuit device shown in
FIG. 1
comprises multi-threshold complementary metal oxide semiconductors (hereinafter also referred to as MT CMOS).
In
FIG. 1
, the reference number
1
designates a two-input NAND gate. Each of the reference numbers
2
and
3
denotes a p channel type metal oxide semiconductor field effect transistor (hereinafter referred to as a p MOS FET). Each of the reference numbers
4
and
5
indicates n channel type metal oxide semiconductor field effect transistors (hereinafter referred to as a n channel MOS FET). In the circuit shown in
FIG. 1
, the absolute value of the threshold voltage of this p MOS FET is set to a low value and the absolute value of the threshold voltage of this n MOS FET is set to a high value. The reference number
6
designates a power source of a predetermined voltage,
7
denotes a ground power source. The reference number
8
indicates a p channel MOS FET connected between the power source
6
and a power source line
12
as a hypothetical power source line. This p channel MOS FET
8
becomes active when a gate terminal of the P channel MOS FET
8
receives a control signal
9
. The reference number
10
indicates an n channel MOS FET connected between ground
7
and a ground line
13
that is a hypothetical ground line. This n channel MOS FET
10
becomes active when a gate terminal of the n channel MOS FET
10
receives a control signal
11
. In this circuit shown in
FIG. 1
, it is formed so that the absolute values of the threshold voltages of the p channel MOS FET
8
and the n channel MOS FET
10
are higher than the absolute values of the threshold voltages of the p channel MOS FETs
2
and
3
and the n channel MOS FETs
4
and
5
forming the two-input NAND gate
1
, respectively.
FIG. 2
is a conventional layout pattern of a memory cell array in a conventional semiconductor integrated circuit device that was disclosed in the patent document of Japanese patent laid open publication number JP-A-8/18021. In
FIG. 2
, the reference number
210
indicates an array section in which a plurality of MOS FETs are arranged in an array form. The reference numbers
220
,
230
,
240
, and
250
denote input/output circuit forming sections located in a peripheral section of the array section
210
, in which input/output circuits are formed. The reference number
260
designates a region in which MOS FETs, each having a high threshold voltage, are formed in the array section
210
. Further, the reference number
270
designates a region in which MOS FETs, each having a low threshold voltage, are formed in the array section
210
.
Next, a description will be given of the operation of the conventional circuit capable of performing under a low supply voltage as the conventional semiconductor integrated circuit device shown in FIG.
2
.
In recent years, there have been significant advancements of technology in portable devices such as mobile telephone devices and the portable devices are widely used in the world. Accordingly, it must be required to operate those portable devices under a lower power voltage in order to maintain the voltage of a battery as long as possible. To reduce the operational voltage used in the portable devices is an effective method to reduce the power consumption of the portable devices as small as possible. Because the power consumption is obtained by multiple of a voltage value and a current value, it is possible to reduce both the voltage value and the current value by reducing the operational voltage of the devices. In general, this method causes to obtain a greatly effect to reduce the power consumption of the devices. However, a MOS FET forming a semiconductor integrated circuit has a drawback in which the operation speed of the MOS FET becomes low according to reducing of the operational voltage. This characteristic of the MOS FET is based on that its threshold voltage is not reduced in proportion to the reducing of the voltage value of the power source. The reason is that the magnitude of a leak current under an off state (an inactive state) of the MOS FET is increased when the threshold voltage of the MOS FET is decreased, so that the power consumption is also increased.
In order to solve the conventional drawback described above, a following conventional method is used.
In the circuit operable under a low voltage shown in
FIG. 1
, when the two-input NAND gate
1
operates, the level of the control signal (CSB
1
)
9
is set to a low level and the control signal (CS
1
)
11
, which is an inverted signal of the control signal (CSB
1
)
9
in voltage level, is set to a high level. Thereby, both the p channel MOS FET
8
and the n channel MOS FET
10
are ON and the voltage potential of the hypothetical power source line
12
rises up to the voltage level of the power source and the voltage potential of the ground line
13
is fallen to the voltage level of the ground GND
7
. As a result, two-input NAND gate
1
operates as a normal NAND gate. In this case, because the threshold voltage of each of the MOS FETs
2
to
5
is set to the low value, it is possible to operate the two-input NAND gate
1
at a high speed when the voltage level of the power source
6
is low.
When the two-input NAND gate
1
is not used, the control signal (CSB
1
)
9
is set to the high level and the control signal (CS
1
)
11
, that is the inverted signal of the control signal (CSB
1
)
9
in voltage level, is set to the low level. At this time, both the p channel MOS FET
8
and the n channel MOS FET
10
become OFF, so that the hypothetical power source lines
12
and the hypothetical ground line
13
are electrically disconnected from the power source
6
and the ground
7
, respectively.
Because it is so formed that the absolute value of the threshold voltage of each of the p channel MOS FET
8
and the n channel MOS FET
10
is higher than that of each of the MOS FETs
2
to
5
, it is possible to suppress the value of the leak current within a lower value.
In general, in a region in which the voltage between the gate and the source of a MOS FET is lower than a threshold voltage of the MOS FET, the magnitude of the leak current flowing through the source and the drain is exponentially increased according to the value of the voltage of the gate. It is therefore possible to greatly reduce the leak current when the MOS FETs
2
to
5
and the MOS FETs
8
and
10
have different threshold voltage values.
Although the above conventional example shows the two-input NAND gate
1
comprising MOS FETs, each having the lower absolute value of the threshold voltage, it is possible to apply the above method to many kinds of semiconductor integrated circuits in size and function such as other logical circuits, memory devices, and the like.
FIG. 2
is the conventional layout of the circuit comprising gate arrays capable of performing under a low voltage as the semiconductor integrated circuit shown in FIG.
1
. In
FIG. 1
, both the p channel MOS FET
8
and the n channel MOS FET
10
, each having a higher threshold voltage, are formed in regions
260
, and the p channel MOS FETs
2
and
3
and the n channel MOS FETs
4
and
5
, each having a lower threshold voltage, are formed in regions
270
that a

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3184904