Dynamic logic circuit with beta controllable noise margin

Details Dynamic logic circuit with beta controllable noise margin Dynamic logic circuit with beta controllable noise margin

1997-03-25

2003-12-23

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S095000

Reexamination Certificate

active

06667637

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to logic circuitry, and in particular, to improving noise margin within a dynamic circuit.
BACKGROUND INFORMATION
Referring to
FIG. 1
, there is illustrated standard domino logic circuit
100
, which has a noise margin that is set predominantly by the threshold voltage of NFET (N-channel field effect transistor)
102
. Actually, the noise margin may be slightly higher due to the half-latch current of PFET (P-channel FET)
105
, but PFET
105
is typically very small. The functionality of circuit
100
is to evaluate data input received by NFET
101
. As an example, the output goes high when the clock signal (CLK) received by NFET
102
is high and the data input signal received by NFET
101
is high. Circuit
100
is reset (output goes low) when the clock signal returns to a low level. This is primarily a result of the receipt of the clock signal by PFET
104
, which raises the node input into inverter
103
to a high level.
Circuit
300
illustrated in
FIG. 3
improves upon the noise margin by introducing PFET
306
directly opposing NFET
301
, which corresponds to NFET
101
. Devices
302
-
305
have corresponding functions to devices
102
-
105
. Circuit
300
is disclosed in cross-referenced U.S. patent application Ser. No. 08/547,269.
However, this solution introduces an undesirable side effect in that circuit
300
may reset depending upon the data input level. More specifically, once circuit
300
has evaluated, it may be reset as a function of the data going low instead of holding its current state until the clock signal goes low. Note that this could occur even for a topology where the device receiving the data input is lower within the “stack” than the device receiving the clock signal. An alternate scheme where the “n” inputs are interchanged is even more obvious.
This results in a slightly different functionality than circuit
100
, and could cause problems in circuit families that use signal pulses for the logic (e.g., four-phase, ripple domino, self-resetting, etc.).
Circuit
300
also has testability problems when the topology is extended to multiplexer structures where multiple n-trees are dotted onto the dynamic node. In the case of multiple n-trees dotted onto the dynamic node, one has to ensure that there are no conflicting DC current paths. This may be a difficult task when the applied patterns are under tester control.
Circuit
200
illustrated in
FIG. 2
solves the data dependent reset problem by eliminating the data restore path once the circuit has evaluated. The noise margin is set by the beta ratio of the pulldown stack of NFETs
201
and
202
against the pullup stack of PFETs
205
and
206
. However, stacking PFETs results in undesired growth to the circuit, since the size of two series PFETs is four times the size of a single PFET for the same strength. In addition to size, performance is degraded due to additional load both on the output and the Data input.
Therefore, there is a need in the art for an improved domino logic circuit that has an improved beta controllable noise margin and which holds its evaluated state until the clock signal goes low.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by providing a logic circuit that includes two NFET devices configured in series for receiving a data input signal, and a PFET device also receiving the data input signal and coupled between a reference voltage source and a node coupling the two NFET devices.
In an alternative embodiment of the present invention, the logic circuit of the present invention may be a multiplexer circuit whereby one or more of the “legs” of the multiplexer circuit implements the present invention.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 4950925 (1990-08-01), Doi et al.
patent: 5065048 (1991-11-01), Asai et al.
patent: 5440243 (1995-08-01), Lyon
patent: 5483181 (1996-01-01), D'Souza
patent: 5525916 (1996-06-01), Gu et al.
patent: 5546022 (1996-08-01), D'Souza
patent: 5572151 (1996-11-01), Hanawa et al.
patent: 5650733 (1997-07-01), Covino

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