Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-11
2003-11-04
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S391000, C257S331000, C257S369000, C257S324000, C257S315000, C257S316000, C257S311000, C257S322000, C257S308000, C257S393000, C438S128000, C438S290000, C438S259000, C438S270000
Reexamination Certificate
active
06642586
ABSTRACT:
This application is based on Japanese Patent Application 2001-031320, filed on Feb. 7, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device for storing data by trapping carriers in the middle layer of a three-layer structure disposed above the channel region of an FET.
2) Description of the Related Art
FIG. 11A
is a cross sectional view showing one example of a conventional flash memory cell. In a surface layer of a p-type silicon substrate
700
, an n-type source region
701
and an n-type drain region
702
are formed. Between the source and drain regions, a channel region
703
is defined. The surfaces of the source and drain regions
701
and
702
are covered with a local oxide film
705
.
On the surface of the channel region
703
, a lamination film (hereinafter called an ONO film)
706
is formed which is made of a lower silicon oxide film
706
A, a silicon nitride film
706
B and an upper silicon oxide film
706
C stacked in this order. A gate electrode
707
is formed on the local oxide film
705
and ONO film
706
.
Next, the operation principle of the flash memory shown in FIG.
11
A will be described.
In writing data, a source voltage Vs to be applied to the source region
701
and a substrate voltage Vsub are set to 0 V, a drain voltage Vd to be applied to the drain region
702
is set to 5 V, and a gate voltage Vg to be applied to the gate electrode
707
is set to 10 V. Channel hot electron injection occurs near the boundary between the channel region
703
and drain region
702
so that electrons are trapped in the silicon nitride film
706
B.
By reversing the voltages applied to the source region
701
and drain region
702
, electrons can be trapped in the silicon nitride film
706
B near the boundary between the channel region
703
and source region
701
. It is therefore possible to store data of two bits in one memory cell.
In reading data, the drain voltage Vd and substrate voltage Vsub are set to 0 V, the source voltage Vs is set to 1V and the gate voltage Vg is set to 3.3 V. In the state that electrons are trapped in the silicon nitride film
706
B, an inversion region of a carrier concentration distribution is not formed in the channel region
703
in its end area on the side of the drain region
702
. Current does not flow through the source and drain. In the state that electrons are not trapped in the silicon nitride film
706
B, drain current flows through the source and drain. Since a depletion region extends from the source region
701
to the channel region
703
near the source region
701
, the drain current is hardly influenced by a presence/absence of trapped carriers on the source region
701
side.
By reversing the source voltage Vs and drain voltage Vd, it is possible to detect whether electrons are trapped in the silicon nitride film
706
B near the boundary between the source region
701
and channel region
703
.
In erasing data, the substrate voltage Vsub is set to 0 V, the source voltage Vs is set to 5 V or a floating state, the drain voltage Vd is set to 5 V, and the gate voltage Vg is set to −5 V. Holes are injected into the silicon nitride film
706
B near the boundary between the drain region
702
and channel region
703
, because of inter-band tunneling. Charges of trapped electrons are therefore neutralized.
By reversing the source voltage Vs and drain voltage Vd, holes can be injected into the silicon nitride film
706
B near the boundary between the source region
701
and channel region
703
.
The density distribution of electrons trapped in the silicon nitride film
706
B by CHE injection has a peak toward the center of the channel region
703
more than the density distribution of holes injected by inter-band tunneling. In order to neutralize charges of electrons distributed toward the center of the channel region
703
, a fairly large number of holes are required to be injected.
As the read/erase operations of a flash memory are repeated, the density distribution of electrons trapped in the silicon nitride film
706
B is considered to extend toward the center of the channel region
703
. Therefore, as the write/erase operations are repeated, it takes a long time to erase data by injecting holes.
During data write, it can be considered that in addition to CHE injection, secondary collision ionized hot electron injection occurs. When secondary collision ionized hot electron injection occurs, electrons are trapped in the silicon nitride film
706
B in an area above the center of the channel region
703
. The electrons trapped in the silicon nitride film
706
B in the area above the center of the channel region
703
cannot be removed by hole injection. Therefore, as the write/erase operations are repeated, the threshold value gradually rises. According to evaluation experiments by the present inventor, although the write threshold value and erase threshold value of a memory cell immediately after manufacture were about 3.8 V and 2.5 V, respectively, the threshold values rose to about 4.6 V and 3.25 V after ten thousands repetitions of the write/erase operations.
FIG. 11B
is a cross sectional view showing a flash memory disclosed in JP-A-9-252059.
In a surface layer of a p-type silicon substrate
710
, an n-type source region
711
and an n-type drain region
712
are formed. Between the source and drain regions, a channel region
714
is defined. At the interface between the drain region
712
and the silicon substrate
710
, an n-type impurity doped region
713
of a low impurity concentration is formed.
A gate insulating film
715
is formed on the surface of the channel region
714
, and on this gate insulating film, a gate electrode
716
is formed. The gate insulating film
715
and gate electrode
716
are disposed spaced apart by some distance from both the source region
711
and drain region
712
. An end portion of the drain electrode
716
on the drain region
712
side overlaps a portion of the low impurity concentration region
713
.
An ONO film
717
covers the side walls of the gate electrode
716
, the substrate surface between the gate electrode
716
and source region
711
, and the substrate surface between the gate electrode
716
and drain region
712
. The ONO film
717
has a three-layer structure of a silicon oxide film
717
A, a silicon nitride film
717
B and a silicon oxide film
717
C. Side wall spacers
718
made of silicon oxide are formed on the surface of the ONO film
717
.
If the impurity doped region
713
of the low impurity concentration is not formed, even if a voltage equal to or greater than the threshold voltage is applied to the gate electrode
716
, a channel is not formed in the substrate surface layer between the gate electrode
716
and drain region
712
. Since the memory cell shown in
FIG. 11B
has the n-type low impurity concentration region
713
, current flows between the source and drain. On the source region
711
side, a depletion layer extends from the source region
711
to the side of the gate electrode
716
so that it is not necessary to form such a low impurity concentration region on this side.
In writing data, a positive voltage is applied to the source region
711
and a higher positive voltage is applied to the gate electrode
716
to make the drain region
712
enter a floating state. Electrons are trapped in the silicon nitride film
717
B on the source region
711
side by avalanche hot electron injection. A voltage of 0 V may be applied to the drain region
712
to utilize CHE injection.
In erasing data, a positive voltage is applied to the source region
711
and a negative voltage is applied to the gate electrode
716
. Holes are trapped in the silicon nitride film
717
B on the source region
711
side by avalanche hot hole injection. Charges of trapped electrons are therefore neutralized. A gate voltage having a larger absolute value may be
Armstrong Westerman & Hattori, LLP
Erdem Fazli
Flynn Nathan J.
Fujitsu Limited
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