Semiconductor memory device including internal power circuit...

Details Semiconductor memory device including internal power circuit... Semiconductor memory device including internal power circuit...

2002-04-12

2003-12-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S226000

Reexamination Certificate

active

06665217

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including an internal power circuit having a tuning function by using a fuse device or the like.
2. Description of the Background Art
In the field of data process and the like, to process data at high speed with lower power consumption, a circuit device called a system LSI (Large Scale Integrated circuit) in which a logic such as a processor and a memory device are integrated on the same semiconductor chip is widely used. In the system LSI, the logic and the memory device are connected to each other by wiring on the chip, so that multi-bit data can be transferred between the logic and the memory device at high speed.
FIGS. 7A and 7B
are diagrams for explaining a conventional layout of an internal power circuit in a semiconductor memory device.
Referring to
FIG. 7A
, a semiconductor memory device
1
has memory arrays
2
a
and
2
b,
a decoder band
3
, and an internal power circuit
4
. Via external pads
5
, external signals are transmitted/received to/from semiconductor memory device
1
mounted on a system LSI, and an external source voltage is supplied to semiconductor memory device
1
. External pads
5
includes a power source pad
5
a
for receiving the supply of an external source voltage Ext.VDD and a signal pad
5
b
via which signals are transmitted/received to/from the outside.
FIG. 7B
is an enlarged view of an area
50
shown in
FIG. 7A
, in which fuse devices FS and internal wiring are disposed.
A plurality of memory cells arranged in a matrix for storing data and peripheral circuits for reading/writing data from/to the memory cells are generically called as memory arrays
2
a
and
2
b.
Decoder band
3
decodes a command control signal and an address signal supplied via signal pad
5
b.
Internal power circuit
4
receives external source voltage Ext.VDD supplied from the outside via power source pad
5
a
and generates internal source voltages for operating memory arrays
2
a
and
2
b.
FIG. 8
is a schematic block diagram showing the configuration of internal power circuit
4
.
Referring to
FIG. 8
, internal power circuit
4
includes a reference voltage generating unit
10
, a memory array voltage (VDDS) generating circuit
20
, a boosted voltage (VPP) generating circuit
30
, and a negative voltage (VBB) generating circuit
40
. Memory array voltage (VDDS), boosted voltage (VPP), and negative voltage (VBB) are collectively called the internal source voltages.
Reference voltage generating unit
10
includes reference voltage generating circuits
12
and
14
. Reference voltage generating circuit
12
receives external source voltage Ext.VDD and generates a reference voltage VREFS as a reference value of memory array voltage VDDS. Reference voltage generating circuit
14
receives external source voltage Ext.VDD and generates a reference voltage VREFP as a reference value of boosted voltage VPP. For example, 3.3V is applied as external source voltage Ext.VDD.
Memory array voltage generating circuit
20
includes a voltage comparator
22
and a driver transistor
25
, and controls the voltage level of an internal power line
27
for supplying memory array voltage VDDS in accordance with reference voltage VREFS. For example, memory array voltage VDDS is set to 2.0 V.
Voltage comparator
22
compares memory array voltage VDDS with reference voltage VREFS. Driver transistor
25
is electrically connected between external source voltage Ext.VDD and internal power line
27
and receives an output of voltage comparator
22
by its gate.
Concretely, when memory array voltage VDDS drops below reference voltage VREFS (2.0 V), an output of voltage comparator
22
is activated to the “L level (logic low)” and driver transistor
25
is turned on. Consequently, an operation current is supplied from external source voltage Ext.VDD to internal power line
27
. On the other hand, when memory array voltage VDDS is higher than reference voltage VREFS, an output of voltage comparator
22
is made inactive to the “H level (logic high)”. In response to this, driver transistor
25
is turned off. As a result, the supply of the operation current to internal power line
27
is stopped.
Boosted voltage generating circuit
30
receives external source voltage Ext.VDD and generates boosted voltage VPP based on reference voltage VREFP. Boosted voltage VPP is used as a gate voltage for turning on a transistor provided to transmit H-level data (memory array voltage VDDS) to a memory cell. It is therefore necessary to set boosted voltage VPP to a voltage higher than a sum of memory array voltage VDDS and a threshold voltage Vth of the transistor. For example, boosted voltage VPP is set to 3.6V.
Boosted voltage generating circuit
30
includes: a voltage divider
32
for dividing a voltage of an internal power line
31
for transmitting boosted voltage VPP; a detecting circuit
34
for comparing voltage VDPP obtained by the dividing operation of voltage divider
32
with reference voltage VREFP; an oscillator
35
which is set in an operative state in accordance with a result of detection of detecting circuit
34
to generate a pump clock; and a charge pump circuit
36
for executing boosting operation in response to the pump clock generated by oscillator
35
.
Voltage divider
32
divides the voltage of internal power line
31
to, for example, ½ and outputs divided voltage VDPP. Detecting circuit
34
receives reference voltage VREFP (1.8 V) determined in consideration of the reference value of boosted voltage VPP and the voltage dividing ratio in voltage divider
32
. When the divided voltage VDPP drops below reference voltage VREFP, oscillator
35
is set in the operative state.
In the operative state, oscillator
35
generates a pump clock and supplies it to charge pump circuit
36
. Charge pump circuit
36
performs charge pumping operation on the basis of the pump clock from oscillator
35
to boost external source voltage Ext.VDD, thereby generating boosted voltage VPP. On the other hand, when boosted voltage VPP is higher than the reference value, oscillator
35
is set in an inoperative state to stop the generation of the pump clock. The voltage boosting operation by charge pump circuit
36
is not therefore executed.
Negative voltage generating circuit
40
receives external source voltage Ext.VDD and generates negative voltage VBB. Negative voltage VBB is used to suppress a leak current in an access transistor of a memory cell. For example, negative voltage VBB is set to −1.0 V.
Negative voltage generating circuit
40
includes a detecting circuit
44
, an oscillator
45
, and a charge pump circuit
46
. When the voltage level of an internal power line
41
for supplying negative voltage VBB exceeds −1.0 V as a reference value, detecting circuit
44
sets oscillator
45
to an operative state.
In an operative state, oscillator
45
supplies the pump clock to charge pump circuit
46
. Charge pump circuit
46
executes a negative charge pump operation on the basis of the pump clock from oscillator
45
to supply negative charges to internal power line
41
. On the other hand, when negative voltage VBB is lower than a reference voltage −1.0 V, oscillator
45
is set in an inoperative state to stop generation of the pump clock. As a result, the supply of negative charges by charge pump circuit
46
is stopped.
With such a configuration, the internal source voltages of memory array voltage VDDS, boosted voltage VPP, and negative voltage VBB can be controlled so as to coincide with reference values.
Since the internal source voltages exert a great influence on the data retaining characteristic of a memory cell and access characteristic, high control accuracy is required. Before the manufacturing stage, an internal power circuit is designed so that the internal source voltages become at desired levels. However, an actually fabricated chip is influenced by manufacture process variatio

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