Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reissue Patent
1995-03-23
2003-11-04
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S379000, C257S750000, C257S754000, C257S758000, C257S371000, C257S390000, C257S510000, C257S734000
Reissue Patent
active
RE038296
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and method for manufacturing the same and particularly to a large scale integrated semiconductor memory and method for manufacturing the same suitable for employment of optical lithography method.
Integration degree of a semiconductor memory is now in the age of 1 Mbits and a 4 Mbits memory is also under the development. Improvement in integration degree has been supported mainly by an ultraminiaturized pattern formation technology, namely the lithography and etching techniques. Therefore, it is very important to acquire the throughput as the lithography technology. For this reason, a reduction projection lithography using optical lenses has been widely employed as a method to form an ultraminiaturized pattern with comparatively high throughput. However, this reduction projection lithography provides a problem that when resolution of lens increases, depth of focus becomes shallow because the light is used and resolution is deteriorated if the surface which becomes the focusing surface (substrate surface is not flat. The optical lithography is explained in the “VLSI Device Handbook”, P139 to 141, issued on Nov. 28, 1983, by Science Forum Co., Ltd.
Meanwhile, as far as element structure is concerned, it is more complicated and the level difference formed on the substrate becomes large. It is because, for example, in the case of DRAM (Dynamic Random Access Memory), a capacitor having a capacitance value larger than the specified value must be formed as a measure for soft error to the &agr;-ray and thereby a stacked capacitor, etc. is used to form a capacitor having a large capacity within a narrow region. (A cell structure using such capacitor is called a stacked capacitor type memory cell (STC memory cell).) This STC memory cell is disclosed in the Published Japanese Patent No. 61-55258.
As explained above, in the reduction projection lithography technology to form an ultraminiaturized pattern, the substrate surface must be formed flat because the depth of focus is shallow. However, in actuality, since there is a large level difference on the substrate as described above, focusing goes out of the depth of focus, resulting in a problem that pattern resolution is deteriorated or size accuracy is lowered.
In order to solve such problems as pattern resolution fault or drop of size accuracy resulting from the level difference on the substrate, a multilayer resist method has been proposed. This multilayer resist method is disclosed, for example, in the Japanese Laid-open patent No. 51-107775. In the case of this method, a flat surface which is not almost effectuated by level difference of substrate is formed with a thick organic film (BL: Bottom Layer) on the substrate having the level difference. Moreover, a shielding layer and a mask layer are sequentially formed thereon, the mask layer is patterned at the upper most layer by the photolithography technology and the shielding layer is etched with the patterned mask layer used as the mask. In addition, with this shielding layer used as the mask, the organic film as the lowest layer is etched by the anisotropic etching such as the sputter etching or ion beam etching, and the layer to be processed is etched with such organic film of the lowest layer used as the mask. Here, a substrate includes a single crystal silicon substrate and insulation film and conductive layer, etc. formed on the surface thereof.
SUMMARY OF THE INVENTION
The inventors of the present invention have found that the multilayer resist method explained above is certainly effective as a measure for the case where level difference exists in the crowded region and also found a problem in this method that a pattern resolution fault or size accuracy deterioration is generated in the memory array region or peripheral circuit region in case level difference is formed between the memory cell array region and peripheral circuit region exists, namely altitude difference exists between regions separated in a certain degree, for example, like the DRAM having the STC memory cell. This problem may be thought to be generated because even if a multilayer resist method is used, altitude difference between the memory array region and peripheral circuit region cannot be eliminated and this altitude difference causes that the surfaces of memory array region and peripheral circuit region are not simultaneously set within the depth of focus of the reduction projection lithography apparatus. According to experiments by inventors of the present invention, in case the altitude difference between two regions is about 1.5 &mgr;m and these regions are separated by 30 to 40 &mgr;m or more, it is difficult even in the multilayer resist method to eliminate such altitude difference.
It is therefore an object of the present invention to provide a technology to process both regions with high accuracy, even if these regions are processed simultaneously, in case these regions are separated by the specified difference and have altitude difference.
It is another object of the present invention to provide a technology to simultaneously process the memory cell array region and peripheral circuit region of a semiconductor memory.
It is another object of the present invention to provide a semiconductor memory wherein a memory cell array region is formed in the recessed part of single crystal silicon substrate and the peripheral circuit region is formed in other part.
The aforementioned and other objects and novel features of the present invention will become apparent from description of this specification and accompanying drawings.
A typical invention among those disclosed in the present application will be summarized and briefly explained hereunder.
Pattern resolution fault of the memory cell array region and peripheral circuit region can be prevented because these are processed within the depth of focus of the exposing apparatus in the exposure process by forming the region which is higher than the semiconductor substrate surface in the finished condition, for example, the memory array region to the recessed part of single crystal semiconductor substrate and the region which is lower than the semiconductor substrate surface under the finished condition, for example, the peripheral circuit region to the other part, with the small altitude difference between the memory cell array region and peripheral circuit region.
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Hasegawa Norio
Kaga Toru
Kawamoto Yoshifumi
Kimura Shin'ichiro
Kure Tokuo
Antonelli Terry Stout & Kraus LLP
Loke Steven
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