Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-17
2003-12-23
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S305000, C257S306000, C257S309000
Reexamination Certificate
active
06667505
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof. More particularly, the present invention relates to an arrangement of capacitors formed above transfer gate in memory cell portion.
2. Description of the Background Art
Conventional semiconductor device is described with reference to
FIGS. 11
to
14
.
FIG. 11
is a plan view of memory cell portion of the semiconductor device. In order to explain relative position of each portion, the drawing assumes that all interlayer insulating layers actually filling spaces between each portion are transparent.
FIG. 12
shows a cross-sectional view cut along a centerline of bit line
6
shown in
FIG. 11
, i.e., a cross-section with respect to the line XII—XII viewed in the direction of arrows.
FIG. 13
shows a cross-sectional view cut along a centerline of capacitor
14
shown in
FIG. 11
, i.e., a cross-section with respect to the line XIII—XIII viewed in the direction of arrows. A plurality of transfer gates
2
are formed linearly and in parallel with each other such that they protrude above the main surface of semiconductor substrate
1
such as silicon wafer. Within a space between these transfer gates
2
, a lower layer contact
4
a
each made of conductive material is formed such that it is connected to each bit line
6
with a regular spacing, to have a shape of approximate ellipse whose major axis is parallel to longitudinal direction of said transfer gate
2
. As shown in
FIG. 12
, lower layer contact
4
a
is electrically connected to main surface of semiconductor substrate
1
. Upper side of transfer gate
2
is covered with an interlayer insulating layer
3
.
As shown in
FIG. 12
, a bit line contact
7
is electrically connected from above lower layer contact
4
a
. Bit line contact
7
is for electrically connecting bit line
6
of conductive material extending horizontally over transfer gate
2
with lower layer contact
4
a
. The section over lower layer contact
4
a
and under bit line
6
is filled with interlayer insulating layer
5
. The section over bit line
6
is filled with interlayer insulating layer
8
.
As shown in
FIG. 13
, a plurality of capacitors
14
arranged over transfer gate
2
are so-called concave type capacitors. These are cup-type condensers each having a bottom surface on its lower end, and its upper ends open. When cut along a horizontal plane, their cross-sectional shape look like two semicircles opposing to each other with a short distance, joined by parallel sides as shown in FIG.
11
. Along this cup-type form, two conductive material parts called storage node
11
and cell plate cylindrical portion
12
contact with an insulating layer (not shown) interposed, forming a condenser. Storage node
11
covers outer side of the cup-type form, and is electrically connected to lower layer contact
4
b
formed inside the space between transfer gates
2
by storage node contact
9
. Therefore, there are two kinds of lower layer contact: lower layer contact
4
a
connecting bit line contact
7
, and lower layer contact
4
b
connecting storage node contact
9
. The section over storage node contact
9
where capacitor
14
does not exist is filled with interlayer insulating layer
10
. Upper surface of interlayer insulating layer
10
is covered with cell plate upper surface portion
13
which is of a conductive material. Cell plate upper surface portion
13
is connected to cell plate cylindrical portion
12
. Cell plate upper surface portion
13
and storage node
11
are insulated by intermediate insulating layer (not shown) interposed therebetween.
This capacitor
14
is a condenser which is desired to have larger capacity. If it has constant thickness (distance from top to bottom in FIG.
13
), it is desirable to enlarge cross-sectional shape of capacitor
14
to obtain larger capacity. In addition, in the case of concave type capacitor, when the aspect ratio as a value of its depth divided by width becomes too large, problem such as defective embedding of electrode material within capacitor
14
or degradation of etching shape may occur. From this aspect, it is also desired to enlarge the cross-sectional shape.
As shown in
FIG. 11
, conventional capacitors
14
are each arranged directly above each storage node contact
9
with its center corresponding to the center of storage node contact
9
; as the result, capacitors are aligned in square.
FIG. 14
extracts and shows only this arrangement of capacitors
14
.
Enlargement of cross-sectional shape of capacitor
14
will be described referring to dimensions a, b, c, and d shown in FIG.
14
. When enlarging the size of individual capacitor
14
with the arrangement of capacitors
14
themselves kept as it is, it is theoretically possible to enlarge two parameters a and b respectively. Processing of capacitor
14
will be difficult, however, if only a becomes longer and the ratio a/b becomes extremely large. Therefore, both a and b must be enlarged together to enlarge the shape of capacitor
14
.
On the other hand, thickness of interlayer insulating layer
10
which separates neighboring capacitors
14
must be larger than a prescribed value to avoid neighboring capacitors
14
effecting each other as condensers. When a and b are enlarged together, d rather than c will become the first problem for the thickness of interlayer insulating layer
10
. Since the distance d must have at least a prescribed value, enlargement of a is limited so that there is a dead space
15
in the area surrounded by four capacitors
14
as shown in FIG.
11
.
Therefore, an object of the present invention is to provide a semiconductor device which can minimize dead space in the arrangement of capacitors and maximize shape of individual capacitor, and a method of manufacturing the semiconductor device.
SUMMARY OF THE INVENTION
To accomplish the above-mentioned object, the semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a plurality of transfer gates formed on the main surface and extending linearly in parallel with each other, lower layer contacts each formed of a conductive material, so as to electrically connect to the main surface in a plurality of spaces respectively formed between the plurality of transfer gates, a plurality of storage node contacts each formed of rod-shaped conductive material extending upwards, and arranged with electrical connection to upper surface of selected ones of the lower layer contacts, and a capacitor formed to have an approximately elliptical cross-sectional shape whose major axis is perpendicular to longitudinal direction of the transfer gate and extending upwards from upper surface of each storage node contact, wherein when the arrangement of the capacitors is seen vertically from above the main surface, rows of capacitors are formed such that, along direction of the major axis, the plurality of capacitors are aligned with regular intervals with a pitch therebetween corresponding approximately two times the sum of width of one transfer gate and width of one space between transfer gates, and when arbitrary one of the capacitor rows is taken as a first capacitor row, a second capacitor row which is another capacitor row is arranged adjacent to and in parallel therewith, and capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by the length corresponding approximately to the sum of width of one transfer gate and width of one space between the transfer gates. In this structure, arrangement of capacitors would not be a simple square-shape, and since neighboring capacitor rows are made out of phase with each other by a certain amount, ellipse of individual capacitor can further be enlarged without interfering with ellipse of each capacitor belonging to the neighboring capacitor row.
In the invention above, preferably, when the storage node contacts aligned with electrical connection to upper surface of each of the lower layer
Narimatsu Koichiro
Shiratake Shigeru
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Thien
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