Memory access system

Details Memory access system Memory access system

1999-09-13

2003-12-09

Lane, Jack A. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S215000

Reexamination Certificate

active

06662292

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory access system particularly but not exclusively designed to facilitate memory accesses in a processor. The invention also relates to a method of generating memory addresses and for accessing memory, to a computer system and a computer program product.
BACKGROUND OF THE INVENTION
Existing computer systems generally operate by generating memory addresses for accessing memory sequentially. That is the architecture of existing computer systems is arranged such that each memory access instruction defines a single memory address. Memory access units exist which allow two addresses to be generated from a single instruction, by automatically incrementing the address defined in the instruction by a certain predetermined amount. However, these systems are clearly restricted in that, if two addresses are generated, the second address necessarily bears a certain predetermined relationship to the first address. Vector stride units also exist which allow more than one memory address to be computed, but these are also limited in the relationship between the addresses. Moreover, it is necessary to generate the first address prior to calculating the second address and therefore it is not possible to generate two memory access addresses simultaneously in a single memory access unit.
It is an object of the present invention to provide increased flexibility for memory accesses.
SUMMARY OF THE INVENTION
According to one aspect of the invention there is provided a memory access system comprising: a register file having a plurality of registers each having the same predetermined bit capacity and capable of holding one or more objects depending on the bit length of the object, said registers including at least a first address register holding at least two packed objects for use in identifying respective memory addresses; a register accessing circuit operative responsive to a memory access instruction to access said first address register in said register file; address generating circuitry for generating at least first and second memory addresses from said at least two packed objects; and memory access circuitry for accessing a memory using said first and second addresses.
In the embodiment described herein, the first address register is an index register, said at least two packed objects being offset objects. The second register holds the base value which, when combined with the packed objects, generates said first and second addresses.
A number of alternatives are possible. According to one alternative, the base value can itself comprise two packed objects which, when combined respectively with the two packed offset objects generate respective first and second addresses.
In another arrangement, the base value can comprise two packed objects, while the index register holds a single offset value which, when added to the respective packed base value objects generate said first and second memory addresses.
The address generating circuitry can comprise first and second addition circuits for respectively adding the packed objects in the first register with the contents of the second register to generate said first and second addresses.
The present invention also provides a computer system comprising: a memory holding data objects; a memory access unit for accessing said memory to retrieve data objects; a decode unit for decoding instructions for use in controlling said memory access unit; and a register file having a plurality of registers each having the same predetermined bit capacity and capable of holding one or more objects depending on the bit length of the objects; said registers including at least a first address register holding at least two packed objects for use in identifying respective memory addresses; wherein the memory access unit is responsive to a memory access instruction defining said first address register to access said first address register in said register file and to generate at least first and second memory addresses from said at least two packed objects, said addresses being used to access said memory.
The length of the object to be retrieved from the memory can be defined in the memory access instruction.
The computer system can contain a second memory access unit which can itself generate two addresses from certain memory access instructions. However, if the second memory access unit is idle and, two addresses have been generated by the first memory access unit, the second memory access unit can receive one of the addresses and use this so that two simultaneous accesses to memory can be made.
The invention also provides a method of generating addresses for accessing a data memory, the method comprising: retrieving from a base register a base value representing at least one base address; retrieving from an index register at least one index value; wherein at least one of the base value and the index value comprises at least two packed objects; combining the base value and the index value to generate at least first and second addresses for accessing said memory; wherein said base register and index register are defined in a single computer instruction.
Another aspect of the invention provides a method of accessing a memory holding data values, the method comprising: reading a memory access instruction which identifies at least a first address register holding at least two packed objects for use in identifying respective memory addresses; simultaneously generating at least first and second memory access addresses from said at least two packed objects; and using said first and second memory access addresses to access said memory.
A still further aspect of the invention provides a computer program product comprising program code means capable of cooperating with a computer when loaded therein to effect memory accesses, said program code means including a memory access instruction which identifies at least a first address register holding at least two packed objects for use in identifying respective memory addresses such that said first and second memory addresses are simultaneously generated by a computer on which the computer program product runs.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.


REFERENCES:
patent: 5924128 (1999-07-01), Luick et al.
patent: 6145077 (2000-11-01), Sidwell et al.
patent: 6260137 (2001-07-01), Fleck et al.
patent: 40 19 961 (1991-01-01), None
patent: 0 047 439 (1982-03-01), None
patent: 0 227 900 (1987-07-01), None

Affiliated with

Also associated with

Rating

Memory access system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory access system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory access system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3183366