Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-06-03
2003-11-11
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S230060
Reexamination Certificate
active
06646932
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2001-168707, filed on Jun. 4, 2001, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor memory devices and more particularly to redundancy systems for relieving or “repairing” defects in memory cells.
2. Description of the Related Art
A redundancy system for use with semiconductor memory chips includes a row redundancy system for repairing defective rows (i.e. rows containing defective cells) and a column redundancy system for repairing defective columns (columns including defective cells), which are typically built together. The row redundancy system is the one that is operatively responsive to input of a row address corresponding to a defective row within a memory array, for providing access to a spare row in lieu of access to such defective row. More specifically, when a row address for selection of a word line containing a defective cell, replacement control is performed in such a way as to activate a spare word line instead of activation of the word line. The column redundancy system is one that is operatively responsive to input of a column address corresponding to a defective column within a memory array while a row corresponding to an input row address within the memory array is accessed (for example, in the state that a word line is activated), for giving access to a spare column in place of access to such defective column. One example is that in a column redundancy system which permits replacement of a column select line (or bit line) with a spare column select line (or spare bit line), replacement control is done for activating a spare column select line (or spare bit line) that performs read/write relative to a spare cell on the accessed row in place of access to such defective column. It is appreciated that the “column select line” is not only a signal line for controlling a column switch which connects a selected bit line with a data line, but also a data line in such a column redundancy system that a defective data line is repaired by another data line.
In this way, the currently available redundancy system is not arranged to perform defective cell replacement by replacement with spare cells on a per-cell basis but is arranged generally to replace a plurality of cells aligned in parallel to a defective cell-containing row or column with a plurality of spare cells within a spare row or spare column. In the rest of the description, an aggregation or assemblage of multiple cells in the direction of a row being subjected to defective cell replacement and a signal line for selecting this will be referred to hereinafter as a “normal row element” or more simply “row element.” An assembly of multiple cells in the direction of a column being subject to defective cell replacement and a signal line for selecting this will be called the “normal column element” or simply “column element” hereinafter. A set of spare cells for use as a defective row/column replacement unit and a signal line for selecting this will be called “redundant element.” In a system for performing defect replacement relative to both rows and columns, both redundant row elements and redundant column elements are provided. Further, the “element” should not be limited only to a set of physically continued cells to be selected by a single signal line and may also be a two-dimensional (2D) aggregation of cells along with a combination or “bundle” of multiple signal lines for selecting them together at a time.
See
FIG. 18
, which shows a redundancy system in one prior known semiconductor memory. A memory array shown herein is subdivided into two, upper and lower memory blocks with a sense-amplifier (S/A) bank interposed therebetween. The lower half memory block includes a redundant row element RELEMENT<0> as disposed therein, which is assigned for replacement of a defective row element found within the lower half memory block. Disposed in the upper half memory block is another redundant row element RELEMENT<1> which is assigned to replacement of a defective row element within the upper half memory block.
The memory array is also bisected laterally into right and left regions as indicated by dotted line in
FIG. 18. A
redundant column element CELEMENT<0> is disposed in the resultant left half region and is assigned to replacement of a column element within the left half region. Disposed in the right region is a separate redundant column element CELEMENT<1> which is assigned to replacement of a defective column element within the right half region.
In this description, an aggregation of normal elements within the memory array which are replaceable by a certain redundant element will be called the relief or “repair” region by means of such redundant element. Repair regions are assigned in units of redundant elements. With the example of
FIG. 18
, row repair regions assigned to the redundant row elements RELEMENT<0>, <1> are upper and lower half ones RRA<0>, <1> of the memory array, respectively; column repair regions assigned to the redundant column elements CELEMENT<0>, <1> are left and right half ones CRA<0>, <1> of the memory array, respectively.
A defective cell in the memory array is replaceable by use of either one of a redundant row element or redundant column element. This means that as shown in
FIG. 18
, a single row repair region must have, without fail, an “overlap region” in which the row repair region at least partially overlaps one or more other column repair regions.
Turning to
FIG. 19
, there is shown a relationship of redundant row and column regions when looking at a single overlap region. Replacement by means of redundancy is to replace defective elements with redundant elements as described previously. In cases where a defective element includes a cell within this overlap region of interest, part of such defective element as included this overlap region will be called the “partial” defective element. In addition, part of the redundant element for replacement of this partial defective element will be called the partial redundant element. Although in
FIG. 19
an exemplary case is shown in which defective cells indicated by markings “x” are present in partial defective row and column elements within an overlap region respectively, the defective cells may exist anywhere at defective elements including partial defective elements—these can be present outside of the overlap region from time to time.
In prior art redundancy systems, the redundant element versus repair region relationship relative to an overlap region is set up so that a redundant row element assigned to a row repair region including such overlap region and a redundant column element assigned to a column repair region including the same overlap region cross or “intersect” each other. The mutual intersection of the redundant row and column elements with respect to the overlap region in this way means that a cell on the redundant column element assigned to the same overlap region is selectable by the redundant row element assigned to such overlap region; similarly, any cell on the redundant row element assigned to the overlap region is selectable by the redundant column element assigned to the overlap region.
The feature of prior art redundancy systems may be reworded in a manner such that the relationship of multiple redundant row elements and redundant column elements on a memory chip versus repair regions to which these are assigned is set to satisfy a condition which follows. All available normal row elements for cell selection within an overlap region being subjected to replacement by means of a certain redundant row element (where, the normal row elements include partial normal row elements within the overlap region, or may be completely included in the overlap region, thereby the partial normal
Kato Daisuke
Watanabe Yohji
Yoshida Munehiro
Kabushiki Kaisha Toshiba
Lam David
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