Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-12
2003-02-11
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S331000, C257S401000
Reexamination Certificate
active
06518624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device and a method for fabricating the same, and more particularly, to a trench-gate power semiconductor device preventing latch-up and a method for fabricating the same.
2. Description of the Related Art
In general, in a power semiconductor device used in high voltage applications, it is very important to prevent latch-up, which causes turn-on of a parasitic transistor existing inside the power semiconductor device. Latch-up can be largely classified into a static latch-up and a dynamic latch-up. The static latch-up is a phenomenon that occurs when a junction between a base region and an emitter region is forward biased during a high current operation in a device in a state in which a voltage is applied to the gate of the device. The dynamic latch-up is a phenomenon that occurs when an impurity type is inverted in an inversion layer during voltage-applied switching at a time when a voltage is applied to a gate or the voltage is removed from the gate, or a phenomenon that occurs due to a displacement current in the base region in a breakdown mode.
FIG. 1
is a sectional view of a conventional power semiconductor device employing a ballast resistor for preventing latch-up.
As shown in
FIG. 1
, the power semiconductor device is, for example, an insulated gate bipolar transistor
10
, realized by a planar process, and the insulated gate bipolar transistor
10
includes a semiconductor substrate
11
formed of a material having first conductivity type impurities, for example, a p-type semiconductor material. A material having second conductivity type impurities, for example, an n-type buffer layer
13
is arranged on the semiconductor substrate
11
. A semiconductor layer
14
used as a drift region is formed on the buffer layer
13
. Although the semiconductor layer
14
also has n-type impurities like the buffer layer
13
, the impurity concentration of the semiconductor layer
14
is lower than that of the buffer layer
13
. P-type base regions
16
extended from part of the upper surface of the semiconductor layer
14
are formed in part of the semiconductor layer
14
. The base regions
16
are formed to be horizontally spaced-apart from one another.
N-type emitter regions
17
with high concentration are formed by being extended from the upper surface of the semiconductor layer
14
in part of the base regions
16
. An inversion layer is formed between the edges of the emitter regions
17
and the base regions
16
. A gate electrode
22
is insulated from the semiconductor layer
14
by a gate dielectric layer
21
. An emitter electrode
23
is formed to be electrically connected to the emitter regions
17
in emitter contact openings
32
. A collector electrode
24
is formed to be electrically connected to the semiconductor substrate
11
.
FIGS. 2A through 2C
are lay-out views illustrating configurations of emitter regions and parts of base regions on the upper surface of the power semiconductor device of FIG.
1
. The same reference numerals as shown in
FIG. 1
denote the same region or layer. Thus, in order to avoid redundancy, a description thereof will be omitted.
First, referring to
FIGS. 2A through 2C
, a gate
22
is formed in a shape having an opening at its center. In the lay-out of
FIG. 2A
, parts
26
of the base region
16
include two adjacent regions surrounded by the emitter regions
17
. Ballast resistors
41
are formed in the emitter regions
17
between the two adjacent parts
26
of the base region
16
. The ballast resistors
41
prevent turn-on of a parasitic transistor by preventing the junction between the base region
16
and the emitter regions
17
from being forward biased. In the lay-out of
FIG. 2B
, emitter contact openings
32
are formed in a “K” shape, and the parts
26
of the base region
16
include three separate regions. The emitter regions
17
surround the separate regions of the parts
26
of the base region
16
. Thus, ballast resistors
42
are formed in the emitter regions
17
between the separate regions of the parts
26
of the base region
16
. In the lay-out of
FIG. 2C
, the emitter contact openings
32
are formed in an “X” shape, and parts
26
of the base region
16
include four separate regions. The emitter regions
17
surround the parts
26
. Thus, ballast resistors
43
are formed in the emitter regions
17
between the parts
26
.
However, although a method for preventing latch-up employing the ballast resistor is effective in preventing the static latch-up, the method is not effective in preventing the dynamic latch-up. Although a ratio in which the stability of the device is decreased by the static latch-up is higher than that of the case in the dynamic latch-up, most of all, in a power semiconductor device in which the stability of the device is very important, destruction of the device by the dynamic latch-up cannot be disregarded. Thus, a countermeasure therefor is required.
Meanwhile, recently power semiconductor devices in which a trench process is implemented, are very important than power semiconductor devices in which the planar process is implemented. The power semiconductor device in which the trench process is implemented can be more highly integrated than a power semiconductor device in which the planar process is implemented. Also, in the power semiconductor device in which the trench process is implemented, since there is no resistance component in a parasitic junction-type field effect transistor (FET), which is an obstacle in improving the characteristics of the power semiconductor device in which the planar process is implemented, the on-resistance of the device is small. However, even in a power semiconductor device in which the trench process is implemented, there are still problems with latch-up.
In the power semiconductor device in which the trench process is implemented, there are some problems in implementing the method for preventing latch-up.
As shown in
FIGS. 2A through 2C
, in the power semiconductor device in which the planar process is implemented, rectangular edges of the opening
32
formed by the gate
22
are obliquely formed to have an incline of about 45°. This is to keep the distribution of a high concentration of p-type impurities in a p-type region (not shown), where the distribution is formed at the center of a cell to reduce the resistance between the base regions
16
and the emitter regions
17
, constant over the entire inversion layer. But, it is not easy for the method for obliquely forming the edges of the gate
22
to be implemented in the power semiconductor device in which the trench process is implemented. This is the reason why the direction of the corners of trenches is different from that of another portions and thus, a gate oxide film is deteriorated. Accordingly, although the ballast resistor is used in the trench-gate power semiconductor device, when the resistance between the base regions
16
and the emitter regions
17
in the corners of a cell is large, this has a bad effect on prevention of latch-up of the device, and thus, improvement thereof is required.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a trench-gate power semiconductor device that prevents latch-up by employing a ballast resistor.
It is another object of the present invention to provide a method for fabricating the trench-gate semiconductor power device that prevents latch-up.
Accordingly, to achieve the above object, there is provided a trench-gate power semiconductor device. The trench-gate power semiconductor device includes a semiconductor substrate of a first conductivity type used as a collector region, a buffer layer of a second conductivity type formed on the semiconductor substrate, a drift region of a second conductivity type formed on the buffer layer, a base region of a first conductivity type formed on the drift region, a gate dielectric layer formed on the surface of a trench which is formed down to
Kim Hyun-chul
Kim Ju-il
Lee Kyu-hyun
Yun Chong-man
Fairchild Korea Semiconductor Ltd.
Loke Steven
Nadav Ori
Rothwell Figg Ernst & Manbeck
LandOfFree
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