Semiconductor constructions

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06653677

ABSTRACT:

TECHNICAL FIELD
The invention pertains to methods of forming semiconductor constructions in which a first semiconductor substrate is bonded to a second semiconductor substrate. The invention also pertains to semiconductor constructions comprising a first semiconductor substrate bonded to a second semiconductor substrate.
BACKGROUND OF THE INVENTION
Technologies referred to as “smart cut” and “wafer-bonding” have been utilized to bond monocrystalline silicon materials onto semiconductor substrates. Smart cut technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized to crack the substrate, and wafer bonding technology generally refers to a process in which a first semiconductive substrate is bonded to a second semiconductor substrate.
In particular applications of smart cut and wafer-bonding technology, hydrogen ions (which can be, for example, H
+
, H
2
+
, D
+
, D
2
+
) are implanted into a first monocrystalline silicon substrate to a desired depth. The first monocrystalline silicon substrate comprises a silicon dioxide surface, and is bonded to a second monocrystalline substrate through the silicon dioxide surface. Subsequently, the bonded first substrate is subjected to a thermal treatment which causes cleavage along the hydrogen ion implant region to split the first substrate at a pre-defined location. The portion of the first substrate remaining bonded to the second substrate can then be utilized as a silicon-on-insulator (SOI) substrate. An exemplary process is described in U.S. Pat. No. 5,953,622. The SOI substrate is subsequently annealed at a temperature of greater than or equal to 900° C. to strengthen chemical coupling within the second substrate.
The present invention encompasses new applications for smart cut and wafer-bonding technology, and new semiconductor structures which can be created utilizing such applications.
SUMMARY OF THE INVENTION
In one aspect, the invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region.
In another aspect, the invention encompasses another method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is bonded to the silicon-containing structures at the upper surface. The second semiconductor substrate comprises a mono-crystalline material. At least one doped silicon region is formed to extend through the monocrystalline material and to electrically contact at least one of the silicon-containing structures.
In another aspect, the invention encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.


REFERENCES:
patent: 4891329 (1990-01-01), Reisman et al.
patent: 5298449 (1994-03-01), Kikuchi
patent: 5374564 (1994-12-01), Bruel
patent: 5374581 (1994-12-01), Ichikawa et al.
patent: 5855693 (1999-01-01), Murari et al.
patent: 5877070 (1999-03-01), Goesele et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5953622 (1999-09-01), Lee et al.
patent: 5998847 (1999-12-01), Assaderaghi et al.
patent: 6004406 (1999-12-01), Kobayashi et al.
patent: 6083324 (2000-07-01), Henley et al.
patent: 6150031 (2000-11-01), Yonehara
patent: 6245161 (2001-06-01), Henley et al.
patent: 6251754 (2001-06-01), Ohshima et al.
patent: 6309945 (2001-10-01), Sato et al.
patent: 6384439 (2002-05-01), Walker
patent: 6423992 (2002-07-01), Fukuda et al.
patent: 6429070 (2002-08-01), Gonzalez et al.
Gösele, U. et al., “Semiconductor Wafer Bonding: Science, Technology, and Applications”, Electrochemical Society Proceedings vol. 97-36, (©1998), pp. 400-425, 436-445.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor constructions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor constructions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor constructions will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3182198

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.