Nonvolatile memory device

Details Nonvolatile memory device Nonvolatile memory device

2001-11-20

2003-11-25

Tran, Thien (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06653685

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having nonvolatile memory cells of multi-storage forms, wherein a structure called “a so-called MNOS (Metal Nitride Oxide Semiconductor)” or “MONOS (Metal Oxide Nitride Oxide Semiconductor)” is configured as a base, and electrons are trapped in nitride near the interface between nitride and oxide at physically different positions, thereby making it possible to perform the storage of multi-valued information, an IC card using the semiconductor device, and a method for manufacturing such a semiconductor device. The present invention also relates to, for example, a technology effective for application to a microcomputer for an IC card provided with a nonvolatile memory of a multi-storage form on an on-chip basis.
A nonvolatile memory cell having a MONOS structure has been described in U.S. Pat. No. 5,768,192. According to this, as illustrated in FIGS.
45
(A) and
45
(B), a gate oxide film
1
and a gate nitride film
2
are laminated on a semiconductor region, and a memory gate electrode
3
, which constitutes a word line, is provided thereon. Further, signal electrodes
4
and
5
either of which serves as a source or drain electrode, are formed in the semiconductor region placed under the memory gate electrode. The present nonvolatile memory cell is capable of trapping electrons in the gate nitride film
2
near the interface with the gate oxide film
1
at physically different positions, thereby performing the storage of multi-valued information. The injection of electrons in nitride is carried out according to channel hot electron injection. When one attempts to inject hot electrons into the right end of the gate nitride
2
as shown in FIG.
45
(A), the left signal electrode
5
is used as a source (source (W)), and the right signal electrode
4
is used as a drain (drain (W)). Further, a drain current is caused to flow so that the direction indicated by arrow W takes the direction of motion of electrons. Thus, the electrons in a channel are accelerated under a high electric field near the drain and thereby brought into hot electrons, followed by injection into the drain end of the gate nitride film
2
. When it is desired to inject hot electrons into the left end of the gate nitride film
2
as shown in FIG.
45
(B), the right signal electrode
4
is used as a source (source (W)) and the left signal electrode
5
is used as a drain (drain (W)), and electrons are moved in the direction indicated by arrow W.
When information stored at the right end of the gate nitride film
2
is read as shown in FIG.
45
(A), the right signal electrode
4
is used as a source (source (R)) and the left signal electrode
5
is used as a drain (drain (R)), and the memory gate electrode
3
may be set to a select level. Since a depletion layer of a MOS transistor expands into the drain side, the switch state of the memory cell greatly depends on the state of a threshold voltage on the source side. Thus, when information stored at the left end of the gate nitride film
2
is read as shown in FIG.
45
(B), the left signal nitride
5
and the right signal electrode
4
are respectively used as a source (source (R)) and a drain (drain (R)) so that the sources and drains are set contrary to FIG.
45
(A), and the memory gate electrode
3
may be set to a select level. If an erase state in which the threshold voltage is lower than the gate select level, is taken, then electrons flow in the direction indicated by arrow R.
A plan view of one memory cell is illustrated in FIG.
45
(C). F means a minimum processed size. FIG.
46
(A) illustrates voltage-applied states necessary for an erase (e.g., electron discharge) operation based on word-line units, FIG.
46
(B) illustrates voltage-applied states necessary for an erase operation based on a memory array batch, FIG.
46
(C) illustrates voltage-applied states necessary for writing (e.g., injection of electrons), and FIG.
46
(D) illustrates voltage-applied states necessary for reading, respectively. In FIGS.
46
(A) through
46
(D), portions indicated by elliptical circles affixed to the memory cells respectively means regions intended for writing, erasing and reading.
SUMMARY OF THE INVENTION
The prior art is not capable of performing writing in plural bit units. Namely, upon the write operation as illustrated in FIG.
46
(C), a bit line
6
is supplied with 3V and a word line
7
is supplied with 6V to carry out hot electron injection. However, if an attempt to carry out byte writing, for example is made, then a write blocking or inhibition voltage of 6V must be applied to the corresponding bit line with respect to a write inhibition bit. In doing so, a large electric field occurs between the bit line and a word line write-unselected at 0V and hence writing is effected on an undesired bit. Since the channel hot-electron injection system is adopted, a write current will increase. Upon the read operation as shown in FIG.
46
(D) as well, it is necessary to set a source line for an adjacent memory cell which shares the use of a bit line
6
between a memory cell selected for the read operation and the adjacent memory cell, to floating (F). There is a possibility that the read operation based on such a virtual ground system will be susceptible to the unbalance of parasitic capacity of the source line brought to the floating and the read operation will be unstable.
As one for solving some of the problems, there is known the preceding application (Unexamined Patent Publication No. 2001-156275, U.S. Ser. or application No. 09/660,923) filed by the present applicant. In a nonvolatile memory cell shown in the present application, as illustrated in FIG.
47
(A), a gate oxide film
11
and a gate nitride film
12
are laminated on a semiconductor region, and a memory gate electrode
13
, which constitutes a word line, is formed thereon. Further, switch gate electrodes
16
and
17
are formed over the semiconductor region on both sides of the memory gate electrode
13
with gate oxide films
14
and
15
interposed therebetween. Signal electrodes
18
and
19
either of which serves as a source or drain electrode, are formed in the semiconductor region lying in the neighborhood below the respective switch gate electrodes
16
and
17
. Since the present memory cell is added with the switch gate electrodes
16
and
17
, a cell size increases correspondingly as illustrated in FIG.
47
(B). Erasing effected on the memory cell is carried out by applying an electric field between the word line (memory gate electrode) and a substrate and drawing electrons into the substrate as illustrated in FIG.
48
(A). Writing is carried out by a source side hot-electron injection system. Namely, as illustrated in FIG.
48
(B), a word line
20
for a write-selected memory cell is set to a high potential to allow a channel current to flow through the memory cell via an on-state switch gate electrode
16
, whereby an electric field is formed between a memory gate electrode
13
, and a substrate and a source electrode
18
. Thus, when the electrons from the signal electrode
18
used as a source electrode pass through a channel narrowed down by the switch gate electrode
16
, they are accelerated and set high in energy. They are further accelerated under a high electric field between the memory gate electrode and the substrate, followed by trapping into the gate nitride film
12
on the signal electrode
18
side used as the source electrode. Since the writing is carried out according to electron source side injection, the source/drain at reading may be the same as at writing. As shown in FIG.
48
(C), a signal electrode
19
may be used as a drain and a signal line
21
may be used as a bit line. W in FIG.
47
(A) means the direction of injection of electrons at writing, R means the direction of motion of electrons at a read operation, and E means the direction of transfer of electrons at erasure. Incidentally, when the electrons are injected into the gate nitride film
12
on the signal electrode
19

Affiliated with

Also associated with

Rating

Nonvolatile memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3181473