Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-08
2003-02-04
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S592000, C438S630000, C438S649000, C438S651000, C438S652000, C438S655000, C438S660000, C438S657000, C438S682000, C257S755000, C257S757000, C257S754000
Reexamination Certificate
active
06514859
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
This present invention relates to a method of forming a salicide. In particular, the present invention relates to a method of forming a salicide with a double gate silicide.
2 Description of Related Art
A conventional transistor comprises a source area, a drain area and a gate area between the source and drain areas.
SUMMARY
The present invention relates to a method of forming a self-aligned silicide (salicide) with a double gate silicide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously thicker than silicide formations over the source and drain areas. The silicide formations formed over the source and drain areas are advantageously shallow, such that the silicide formations do not impede the junction and cause current leakage.
One aspect of the invention relates to a method of forming a silicide. The method comprises forming a barrier dielectric layer over a gate area, a source area and a drain area. A portion of the barrier dielectric layer is removed to expose at least the top of the gate area. A first metal layer is formed over the gate area and the barrier dielectric layer. A first thermal anneal is applied that causes the first metal layer to at least partially react with the gate area to form a first silicide layer over the gate area. Any unreacted metal from the first metal layer is removed. The barrier dielectric layer over the source and drain areas is removed. A second metal layer is formed over the first silicide layer and the source and drain areas. A second thermal anneal is applied, wherein the second thermal anneal causes (1) the second metal layer to react with the gate area to enhance the first silicide layer, and (2) the second metal layer to at least partially react with the source and drain areas to form second and third silicide layers. Any unreacted metal from the second metal layer is removed.
Another aspect of the invention relates to a product made by the method above.
The present invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.
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Erhardt Jeff
Paton Eric
Lee Hsien Ming
Pham Long
Skjerven Morrill LLP
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