Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
1999-10-11
2003-02-25
Lee, Thomas (Department: 2154)
Electrical computers and digital processing systems: support
Computer power control
C713S600000, C713S601000, C712S223000, C712S224000, C712S225000, C712S226000
Reexamination Certificate
active
06526514
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to computers and more particularly to processing interrupts therein.
BACKGROUND OF THE INVENTION
Computers are known to include software and hardware. The hardware includes a central processing unit (CPU), system memory, a memory interfacing chipset, video graphics processing circuitry, and input/output ports. The software includes an operating system (e.g., Windows 98™), drivers, application interfaces (API), and a plurality of applications (e.g., word processing, spreadsheets, drawings, games, etc.). Such software and hardware work in concert to provide a user with a very powerful tool.
To ensure that the computer operates properly, it periodically interrupts the current processing of an application for system level verifications to ensure proper behavior of the computer. Such system level interrupts include system management interrupts (SMI) and non-maskable interrupts (NMI), which provide system level functions such as close/open door, fan on/off, start/stop clocks, turn-on/off power supply, hardware initialization (HW INIT), power management interrupts, etc. The computer also processes application level interrupts, which are initiated by internal or external devices of the computer. For example, a device coupled to the PCI bus of the computer may initiate an interrupt requesting access to a PCI bus. Alternatively, an interrupt may be received via an Internet connection, an Ethernet connection, etc.
FIG. 1
illustrates the relevant portions of a computer for processing both system level interrupts and application, or device, level interrupts. Such relevant portions include a south bridge, north bridge (which comprise the memory interfacing chipset), and a central processing unit. The south bridge includes a hard-coded interrupt controller and an interrupt state machine. The interrupt controller is operably coupled to receive external device interrupts, or application level interrupts. The interrupt state machine is operably coupled to receive system event interrupts, i.e., system level interrupts. The interrupt state machine processes the system event interrupts by detecting initiation of a system level interrupt and providing information to the interrupt controller as to which particular system level interrupt has been initiated. The interrupt controller processes the system level interrupt as a system management interrupt. The interrupt controller also processes the application level interrupts (i.e., the external device interrupts) as non-maskable interrupts. Note that in many systems, the system level and application level interrupts may be processed as non-maskable interrupts.
The system management interrupts and/or the non-maskable interrupts are provided to the central processing unit for processing. Upon receipt of an interrupt, the central processing unit stops its current processing to perform the interrupt. Note that based on the context of the central processing unit, it may be a very inopportune time to process the interrupt. For example, depending on the particular action, i.e., context, of the central processing unit, processing should not be interrupted. For example, generating display data, receiving Ethernet data, modem signals, etc. Nevertheless, when the central processing unit is in one of these contexts and an interrupt is received, the processing of these certain function is stopped and the interrupt is processed. As such, data may be lost and/or corrupted.
The central processing unit is shown to include a gate, which is operably coupled to receive a hardware initialization system level interrupt. The hardware initialization interrupt is used to reset caches within the central processing unit and may also be used to reset registers within the central processing unit. As such, the hardware initialization interrupt, resets the central processing unit by overriding any data stored within the cache and/or registers which may cause loss of data if not properly executed.
While the computer of
FIG. 1
processes system level and application, or device, level interrupts fairly well, a hard coding of the interrupt controller fixes the priority scheme for processing the interrupts. As such, changes to prioritization of interrupt processing can only be achieved by hard wire changes, which cannot be effectively done in an operational setting. Thus, a computer must function in accordance with the hard coded interrupt prioritization scheme even though, under certain operating conditions, it is not the most efficient scheme.
In addition, the interrupt processing does not allow the central processing unit to customize power down and/or power savings interrupt for more efficient restarts. Further, the interrupt processing does not allow for interprocessor interrupts or intraprocessor interrupts. Such features would provide the computer architect greater flexibility in designing a computer that more efficiently processes interrupts under all operating conditions.
Therefore, a need exists for a method and apparatus for processing interrupts in a dynamic manner that allows for power management customization, interrupt processing customization, interprocessor interrupts and intraprocessor interrupts.
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patent: 5375211 (1994-12-01), Maruyama et al.
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patent: 5771373 (1998-06-01), Kau et al.
patent: 5889973 (1999-03-01), Moyer
Alasti Ali
Nguyen Nguyen Q.
ATI International SRL
Hu Jinsong
Lee Thomas
Vedder Price Kaufman & Kammholz
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