Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-19
2003-11-11
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000
Reexamination Certificate
active
06646299
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit configuration, that is to say a circuit configuration which is provided in a substrate, wherein the integrated circuit configuration includes at least two capacitors. The invention further relates to a method of producing such an integrated circuit configuration.
Such an integrated circuit configuration is, for example, a DRAM (Dynamic Random Access Memory) cell configuration with memory cells which have a capacitor and a transistor connected thereto. The information of the memory cell is stored in the form of a charge in the capacitor. When the transistor is driven via a wordline, the charge of the capacitor can be read out via a bit line.
In order to increase the capacitance of the capacitor while the capacitor at the same time requires little space, it is proposed, for example, in H. Horii et al. “A Self-aligned Stacked Capacitor using Novel Pt Electroplating Method for 1 Gbit DRAMs and Beyond”, Symposium on VLSI Technology Digest of Technical Papers (1999), 103, to use barium-strontium-titanate (BST) as the capacitor dielectric. BST has a very high dielectric constant. Platinum is used as the material of a cylindrical first capacitor electrode of the capacitor. Because platinum is difficult to structure through the use of dry etching, the first capacitor electrode is grown through the use of electroplating. For this purpose, a depression is produced in a first insulating layer. A 40 nm thick adhesive layer made of ruthenium is then deposited. A second insulating layer is then produced and patterned in such a way that the depression is exposed. As a result of electroplating, platinum grows on the adhesive layer and fills the depression in the first insulating layer and in the second insulating layer. The parts of the adhesive layer which expose the second insulating layer are then removed. To produce a capacitor dielectric, BST is then applied to a thickness of 40 nm by sputtering. No information is given on the necessary second capacitor electrode.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit configuration with at least two capacitors which overcomes the above-mentioned disadvantages of the heretofore-known integrated circuit configurations of this general type and which can be manufactured without dry etching of metal which is difficult to etch in order to produce capacitor electrodes, and which allows to form the capacitor dielectric of a perovskite. It is a further object of the invention to provide a method of manufacturing such an integrated circuit configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration, including:
a substrate having a surface;
at least two capacitors provided on the surface of the substrate;
each of the capacitors having a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric;
the first capacitor electrode and at least a given part of the second capacitor electrode having respective lateral faces, the first capacitor electrode and the second capacitor electrode being disposed such that only the respective lateral faces of the first capacitor electrode and of at least the given part of the second capacitor electrode are opposite one another;
the first capacitor electrode and the given part of the second capacitor electrode being composed of a material that is hard to etch;
the capacitor dielectric being composed of a perovskite and being disposed between the lateral faces of the first capacitor electrode and of the given part of the second capacitor electrode disposed opposite one another;
the first capacitor electrode being substantially composed of a given metal, the second capacitor electrode being configured such that only the given part of the second capacitor electrode is substantially composed of the given metal;
an adhesive layer being composed of at least of one material selected from the group consisting of ruthenium, iridium, molybdenum, a ruthenium oxide, an iridium oxide, a molybdenum oxide, Tantalum and TaN, the adhesive layer having a first part and a second part;
the first capacitor electrode being disposed on the first part of the adhesive layer and the second capacitor electrode being disposed on the second part of the adhesive layer; and
the given part of the second capacitor electrode of a first one of the at least two capacitors being coherent with the given part of the second capacitor electrode of a second one of the at least two capacitors.
According to another feature of the invention, the first capacitor electrode has an upper end; the second capacitor electrode has an upper end and a lower end; the lateral faces of the first capacitor electrode of the at least two capacitors extend substantially perpendicularly with respect to the surface of the substrate and extend from the upper end of the first capacitor electrode to the lower end of the second capacitor electrode; and the lateral faces of the given part of the second capacitor electrode of the at least two capacitors extend, from the upper end of the second capacitor electrode, substantially perpendicularly with respect to the surface of the substrate.
According to yet another feature of the invention, the given part of the second capacitor electrode laterally surrounds the first capacitor electrode.
According to another feature of the invention, a filling structure is disposed between the first part of the adhesive layer and the second part of the adhesive layer; and the capacitor dielectric is disposed on the filling structure.
According to a further feature of the invention, a semiconductor component is disposed under the first capacitor electrode; the first capacitor electrode being connected to the semiconductor component; and the first capacitor electrode, the second capacitor electrode, the capacitor dielectric, and the semiconductor component forming, for each of the at least two capacitors, respective memory cell configurations.
According to another feature of the invention, the memory cell configurations are configured substantially identical to one another and form a memory cell array.
With the objects of the invention in view there is also provided, a method for producing an integrated circuit configuration including at least two capacitors, the method includes the steps of:
applying an adhesive layer on a substrate;
subsequently applying an auxiliary layer on the substrate;
forming a first depression and a second depression in the auxiliary layer such that the first depression and the second depression extend as far as the adhesive layer;
producing, with an electroplating process, a first capacitor electrode in the first depression on a first part of the adhesive layer, and at least part of a second capacitor electrode in the second depression on a second part of the adhesive layer;
removing the auxiliary layer;
subsequent to removing the auxiliary layer, removing parts of the adhesive layer, which have been exposed by removing the auxiliary layer, by an an isotropic etching step; and
producing a capacitor dielectric between the first capacitor electrode and the part of the second capacitor electrode.
Another mode of the method according to the invention includes the steps of:
subsequent to removing the parts of the adhesive layer which have been exposed by removing the auxiliary layer, producing at least one filling structure such that the at least one filling structure divides the first part of the adhesive layer from the second part of the adhesive layer; and
producing the capacitor dielectric on the at least one filling structure.
Another mode of the method according to the invention includes the step of producing the second depression such that the second depression laterally surrounds the first depression.
Yet another mode of the method according to the invention includes the steps of producing a semiconductor component of the integrated circuit configuration prior to producin
Hierold Christofer
Willer Josef
Mayback Gregory L.
Nguyen Cuong Quang
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