Bus system

Details Bus system Bus system

2001-03-27

2003-12-30

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Access arbitrating

Access prioritizing

C710S107000, C710S036000, C710S041000, C710S240000, C710S241000, C710S058000

Reexamination Certificate

active

06671761

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus system, and more particularly, to a bus system in which efficiency for a data bus is improved by adjusting the order of execution of access commands and the point in time and order of execution of access commands delivered to each slave device. The present application is based on Korean Patent Application No. 2000-46658, which is incorporated herein by reference.
2. Description of the Related Art
An arbiter is used to arbitrate access to a bus. In conventional bus systems, an arbiter receives requests for access to a bus from a plurality of master devices, arbitrates the bus access requests according to a specific arbitration algorithm, and grants control of the bus to the master devices (“masters”) based on the arbitration result. Once a master's request has been granted, the master may take control of the bus until the master has completed its transfer of data with a corresponding slave device. Here, the bus may include an address/control bus and a data bus.
A currently used bus system adopts a high-speed memory such as synchronous DRAM (SDRAM) as a slave device. In the case of high-speed memory such as SDRAM, it does not access an access/control bus concurrently with a data bus. That is, if an address/control signal such as an address or read/write flag is input to SDRAM, data is output or input after a predetermined latency period has lapsed. Thus, a master device actually takes control of an address/control bus or a data bus for a shorter period than is expected. According to the conventional arbitration system in which access to or control of both address/control bus and data bus is granted simultaneously for a predetermined time, there are a large number of idle clock cycles of the address/control bus and data bus, which degrades the efficiency of bus access.
An arbiter adopting the fixed priority scheme is simple to design, but the arbiter cannot be employed if the priority level assigned needs to be modified during operation of a bus system. Arbitration according to the priority designation scheme is advantageous in supporting a master device which frequently transmits and receives data across a bus, if necessary.
However, the priority designation scheme has a problem in that hardware is large and complicated compared to a fixed priority scheme or a round robin algorithm giving each master device equal chances to access or control the bus. More specifically, the priority designation is performed by comparing each input port, to which a bus request is input from each master device, to look for the input port having the highest priority. Thus, for example, if the number of input ports is 3 or 4, three or six comparators are needed. That is, a number nC
2
of comparators are needed for a number N of input ports, where nC
2
represents “n(n−1)
!”. An increase in the number of master devices increases the number of comparators significantly, which may result in an extremely large arbiter circuit and slow arbitration speed. As a consequence, to achieve an arbiter circuit of an appropriate size and high arbitration speed, the number of master devices must be restricted.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a bus system having improved data transfer efficiency by reducing the number of idle clock cycles of a data bus.
It is another objective of the present invention is to provide an arbiter providing a priority designation scheme without restriction on the number of master devices, and a bus system using the arbiter.
Accordingly, to achieve the above objectives, the present invention provides a bus system including a plurality of master devices and a plurality of slave devices, at least one of the slave devices having a latency period. The bus system includes: an arbiter that receives access commands output from the plurality of master devices and outputs the access commands in an order according to a predetermined arbitration algorithm; an execution scheduler that receives the access commands from the arbiter and outputs the access commands in the order in which execution preparation by corresponding slave devices are complete; a plurality of command execution controllers corresponding to at least one of the slave devices, respectively, each command execution controller stores two or more access commands input from the execution scheduler, extracts access information necessary for execution from the stored access commands, controls the output order of the access commands based on the result of comparing the extracted access information to access information from the command currently being executed, so that the total execution time of the stored commands is shorter than the total execution time according to the order in which the commands are input; and a plurality of pseudo-delayers corresponding to at least one of slave devices, respectively, each pseudo-delayer delays and outputs the access command received from the command execution controller to a corresponding slave device so that the latency period of the corresponding slave device may equal the longest of latencyperiods of the plurality of slave devices.
The arbiter includes a bus request receiver, connected to the plurality of master devices, for receiving bus request inputs from the master devices, a priority level extractor for outputting priority level signals indicating predesignated priority levels corresponding to the master devices if the bus requests are input through the bus request receiver, and generating a priority level summation signal indicating all priority levels of the bus requests based on the output priority level signals, a priority output unit for outputting priority levels in order of decreasing priority based on the priority level summation signal generated by the priority level extractor, a priority mapper, including an identifier output unit for outputting identifiers of the master devices submitting bus requests based on the priority level signals, and an arbitration circuit that grants bus access to the master device having the identifier output from the priority mapper in order for the master device granting the bus access to output the access command.
Preferably, the bus request receiver comprises a plurality of input ports connected to the plurality of master devices for receiving bus request inputs from the master devices, and a plurality of registers provided in the input ports for storing priority levels designated at the input ports.
Preferably, the priority level signal is represented using the same number of bits as the priority level. The priority level extractor performs an OR operation on one or more priority level signals on a bit-by-bit basis and generates the priority level summation signal, which is represented in the same number of bits as the priority level signal. The OR operation is based on negative logic.
Preferably, the master device identifier output unit includes an identifier extractor that generates an identifier signal by extracting a bit column including a bit indicating a priority level requested from a matrix constructed of the priority level signals and extracts a corresponding master device identifier based on the generated identifier signal, and an identifier output unit that outputs an identifier of the master device having the priority level output from the priority output unit, wherein the identifier is one of the identifiers extracted by the identifier extractor. The identifier extractor includes decoders that receive input identifier signals and extract corresponding master device identifiers.
Preferably, the execution scheduler includes an access command distributor that receives the access commands output from the arbiter and transmits the access commands to the corresponding command execution controllers, and an execution scheduling unit that send outs an execution starting signal of the transmitted access command to the command execution controller corresponding to t

Affiliated with

Also associated with

Rating

Bus system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3178144