Tracking bin split technique

Details Tracking bin split technique Tracking bin split technique

2001-03-28

2003-11-25

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S600000, C710S061000, C709S241000

Reexamination Certificate

active

06654899

ABSTRACT:

FIELD
The present invention relates to a tracking bin split technique and more particularly, the present invention relates to a tracking bin split technique for generating high frequency clocks used in processors.
BACKGROUND
In many applications, a circuit board, such as a motherboard, has a board clock generator disposed thereon. The board clock generator is used to generate clocks which are distributed to various elements mounted on the board. This insures that the elements mounted on the board operate in a substantially synchronous fashion. Quite often, certain elements, such as high-speed processors, will operate at a clock speed which is significantly higher than that of the board clock generator clocks. Accordingly, it is necessary to employ a bin split technique to produce a clock which is an integral multiple of the board clock generator clock and to distribute this clock to various elements within a processor.
FIG. 1
is a block diagram illustrating an example of a disadvantageous bin split arrangement for generating a clock output whose frequency is an integral multiple of the board clock generator clock. As shown in
FIG. 1
, a board clock generator
100
, disposed on a motherboard, outputs a clock XCLKREF which is inputted to a core clock generator
110
, contained within a processor chip, for example, disposed of the motherboard. Contained within the core clock generator
110
is a PLL (Phase Locked Loop)
120
connected to a PLL Feedback Divider (1/2N)
130
and a PLL Output Divider (1/2)
140
.
The output of the PLL
120
is fed back to one input thereof via the PLL feedback divider (1/2N)
130
. The PLL feedback divider (1/2N)
130
divides the frequency outputted by the PLL
120
by 2N. It the frequency of the clock outputted by the board clock generator
100
is equal to Fref, then the output of the PLL
120
is a clock F whose frequency is equal to 2N×Fref. The clock F outputted by the PLL
120
is then inputted to the PLL Output Divider (1/2)
140
which produces an output clock Fcore whose frequency is equal to N×Fref.
As illustrated in
FIG. 1
, the input reference clock XCLKREF is a constant frequency signal that is generated by the board clock generator
100
and a directly drives the PLL
120
of the processor. The PLL
120
output frequency is a product of the reference clock frequency and the PLL
120
divider ratio and the core frequency bin split is equal to the reference clock frequency. Due to the constant reference frequency, in order to generate higher core frequencies, a higher divider ratio must be used. Increasing the PLL divider ratio (2N) increases the PLL sensitivity to noise due to the decreasing of the PLL damping factor. Because of this, a higher core clock signal jitter occurs at higher core frequencies.


REFERENCES:
patent: 4180783 (1979-12-01), Ehalifa
patent: 5142247 (1992-08-01), Lada, Jr. et al.
patent: 5627538 (1997-05-01), Ferry
patent: 5742208 (1998-04-01), Blazo
patent: 5786732 (1998-07-01), Nielson
patent: 6025738 (2000-02-01), Masleid
patent: 6137336 (2000-10-01), Baba et al.
patent: 6188258 (2001-02-01), Nakatani

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