Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2002-10-17

2003-11-04

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257S319000

Reexamination Certificate

active

06642571

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically, it relates to a nonvolatile semiconductor memory.
2. Description of the Background Art
A nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) has recently been watched with interest as a semiconductor memory substitutional for a magnetic memory such as a hard disk or a floppy disk.
A memory cell of an EPROM or an EEPROM stores carriers in a floating gate electrode for storing data in response to presence/absence of the carriers and reading the data by detecting change of a threshold voltage responsive to presence/absence of the carriers. In particular, the EEPROM includes a flash EEPROM erasing data in the overall memory cell array or dividing the memory cell array into arbitrary blocks and erasing data in units of the blocks. This flash EEPROM, also referred to as a flash memory, can attain a large capacity, low power consumption and a high-speed operation, and is excellent in shock resistance. Therefore, the flash EEPROM is used in various portable devices. Further, memory cells of the flash EEPROM can advantageously be more easily integrated as compared with those of the EEPROM.
In general, a stacked gate memory cell and a split gate memory cell are proposed as memory cells forming a flash EEPROM.
In a write operation of storing electrons in a floating gate of a stacked gate memory cell, electrons stored in a channel of a semiconductor substrate are converted to hot electrons, which in turn are injected into the floating gate electrode. At this time, a voltage of 10-odd V to a control gate electrode. In an erase operation of extracting electrons stored in the floating gate electrode of the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) is fed from a source region to the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the source region.
In a write operation of storing electrons in a floating gate electrode of the split gate memory cell, electrons stored in a channel of a semiconductor substrate are converted to hot electrons, which in turn are injected into the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a source region. In an erase operation of extracting electrons from the floating gate electrode of the stacked gate memory cell, an F-N tunnel current is fed from a control gate electrode to the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the control gate electrode.
Thus, hot electrons are employed for injecting electrons into the floating gate electrode in the write operation and the F-N tunnel current is employed for extracting the electrons stored in the floating gate electrode in the erase operation in the conventional stacked or split gate memory cell.
In order to hold the carriers stored in the floating gate electrode over a long period, the thickness of an insulator film enclosing the floating gate electrode must be increased. However, the hot electrons or the F-N current is utilized for injecting or extracting the electrons into or from the floating gate electrode. Therefore, the voltage (hereinafter referred to as an operating voltage for the memory cell) applied to the control gate electrode or the drain region in the write or erase operation must be increased as the thickness of the insulator film enclosing the floating gate electrode is increased.
The operating voltage for the memory cell is generated in a step-up circuit. In this case, a practical voltage is up to 10-odd V. When a silicon oxide film is employed as the insulator film enclosing the floating gate electrode and the operating voltage for the memory cell is set to 10-odd V, however, it is difficult to increase the thickness of the silicon oxide film beyond 10 nm. In general, therefore, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to not more than 10-odd nm, in order to suppress the operating voltage for the memory cell to 10-odd V. It is known that the electrons stored in the floating gate electrode can be held for a period practically satisfiable to some extent if the thickness of the silicon oxide film is at least 8 nm.
Also when holes are stored in the floating gate electrode, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to not more than 10-odd nm thereby suppressing the operating voltage for the memory cell to not more than 10-odd V while holding the holes stored in the floating gate electrode for a period practically satisfiable to some extent, similarly to the aforementioned case of storing electrons.
The flash EEPROM is recently required to attain a lower voltage, a higher operating speed, lower power consumption and higher integration while ensuring a sufficiently long holding time (at least 10 years) for carriers stored in the floating gate electrode.
As hereinabove described, the thickness of the silicon oxide film must not be reduced below 8 nm in general, in order to ensure a carrier holding time of at least 10 years when employing the silicon oxide film as the insulator film enclosing the floating gate electrode.
When the operating voltage for the memory cell is reduced, the step-up time (lead time) can be reduced for increasing the speed for a write operation and an erase operation. Further, power consumption can also be reduced.
The circuit scale of the step-up circuit for generating the operating voltage for the memory cell is increased as the level of the generated voltage is increased. An area (transistor size) of a substrate occupied by a transistor forming a peripheral circuit (a decoder, a sense amplifier, a buffer or the like) for the flash EEPROM is increased as the withstand voltage is increased. When the operating voltage for the memory cell is reduced, therefore, the circuit scale of the step-up circuit as well as the size of the transistor forming the step-up circuit are reduced, whereby higher integration can be attained.
Therefore, a high-speed operation, low power consumption and high integration can be simultaneously implemented by reducing the operating voltage for the memory cell.
Also generally known is a split gate flash EEPROM capacitively coupling a source diffusion layer with a floating gate thereby controlling the potential of the floating gate by the potential of the source diffusion layer. According to this structure, the source diffusion layer is capacitively coupled with the floating gate, while a control gate is also capacitively coupled with the floating gate. In this case, the control gate covers the upper portion and the side surface of the floating gate in the structure of the conventional split gate flash EEPROM, leading to large opposite areas of the control gate and the floating gate. Therefore, the coupling ratio between the control gate and the floating gate is increased to some extent. Thus, the coupling ratio between the source diffusion layer and the control gate is relatively reduced, and hence a high voltage must be applied to the source diffusion layer in order to control the potential of the floating gate by the potential of the source diffusion layer. Consequently, it is difficult to reduce the operating voltage in the conventional split gate flash EEPROM controlling the potential of the floating gate by the potential of the source diffusion layer.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory capable of achieving a high-speed operation, low power consumption and high integration by increasing the life of the semiconductor memory and reducing the voltage therefor.
Another object of the present invention is to increase the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a c

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