Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-09-26
2003-10-14
Dharia, Rupal (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S306000, C710S110000
Reexamination Certificate
active
06633936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of bus interfaces, and more particularly, to retry mechanisms in bus interfaces.
2. Description of the Related Art
Generally, devices in a system may use a bus to communicate. Particularly, it is frequent that a variety of peripheral devices are coupled to a bus (e.g. the Peripheral Component Interconnect bus, or PCI bus) for communicating with other devices (either directly connected to the bus or indirectly through one or more bus bridges). The bus is a shared resource among the devices coupled to the bus, and thus efficient use of the bandwidth available on the bus may be important to overall system performance. During the time that a transaction is active on the bus, other transactions may be precluded from being initiated or completing. For example, the PCI bus is a shared address/data bus in which the address and data are transferred on the same lines (but at different times). A transaction initiated on the PCI bus consumes bus bandwidth until the data is transferred or until the transaction is retried. Other buses may implement separate address and data buses, but even these buses may have wasted bandwidth. For example, if the data bus is granted to a transaction, the transaction consumes data bus bandwidth until the data is actually transferred.
In order to enforce efficient bandwidth usage, some buses (such as the PCI bus) may specify a maximum latency that a target device may delay before performing at least the first data transfer of a read transaction. If the target device cannot transfer data within the maximum latency, then the target device must retry the transaction (thus freeing the bus for use to perform another transaction). In the time between the retry and the subsequent reattempt of the transaction by the initiating device, the target device may continue to make progress toward being able to transfer data. For example, for a read transaction, the target device may continue to fetch the requested data internally.
Many PCI bus devices currently implement a static counter which counts to a timeout value (e.g. the maximum specified latency or some predetermined latency less than the maximum latency) and, if the timeout is reached without data available for transfer, the PCI device retries the transaction. Other PCI devices (particularly long latency devices) may implement a policy of always retrying a read transaction the first time the read transaction is presented on the PCI bus, and initiating an internal read to begin fetching the requested data. Still further, other devices may implement each of the above policies, selectable as modes for the device under software control.
Unfortunately, the aforementioned mechanisms tend to be wasteful of PCI bus bandwidth. A more efficient retry mechanism is therefore desired.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an adaptive retry mechanism described herein. The mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. Since the selected retry latency is based on the latencies currently being experienced in the system, the retry latency may be dynamically adjusted to more efficiently use bus bandwidth. In one embodiment, the mechanism may be used on the PCI bus although any bus which allows for retry of transactions may employ the mechanism.
The recorded latencies may be measured directly during the recent transactions, or the latencies may be calculated or estimated from multiple internal states of the system. For example, in one embodiment, the latencies may be calculated based on the memory controller's memory read latency, the number of transactions queued in the memory controller, and the amount of traffic on the system bus. The number of transactions queued in the memory controller may increase the latency for a particular transaction since some or all of the queued transactions may be performed by the memory controller prior to the particular transaction. The amount of traffic on the system bus may increase the latency for a particular transaction by delaying access to the bus in response to the particular transaction.
In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected, thus avoiding retrying transactions just before the data arrives. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected, thus more rapidly retrying transactions and therefore freeing bus bandwidth for other transactions.
Broadly speaking, a method is contemplated. Latencies of transactions on a bus are determined. Each latency represents a time period from a first event of a corresponding transaction to a second event of the corresponding transaction. A first retry latency for a first transaction is selected from a plurality of retry latencies responsive to latencies of N previous transactions (N is a positive integer). The first retry latency is indicative of a point in time, measured from the first event of the first transaction on the bus, that the first transaction is retried on the bus if the second event of the first transaction does not occur before the point in time.
Additionally, an apparatus is contemplated, comprising a buffer and a circuit coupled to the buffer. The buffer is configured to store latencies of transactions on a bus, each of the latencies representing a period of time from a first event of a corresponding transaction to a second event of the corresponding transaction. The circuit is configured to select a first retry latency for a first transaction from a plurality of retry latencies responsive to latencies of N previous transactions, wherein N is a positive integer. The first retry latency is indicative of a point in time, measured from the first event of the first transaction on the bus, that the first transaction is retried on the bus if the second event of the first transaction does not occur before the point in time.
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Chui Kwong-Tak A.
Hayter Mark D.
Keller James B.
Ning Chun H.
Broadcom Corporation
Dharia Rupal
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Vu Trisha
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