Semiconductor memory device internal voltage generator and...

Details Semiconductor memory device internal voltage generator and... Semiconductor memory device internal voltage generator and...

2002-03-28

2003-10-21

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S189070, C365S189090, C327S530000, C327S538000

Reexamination Certificate

active

06636451

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an internal voltage generator of a semiconductor memory device and an internal voltage generating method thereof.
2. Description of the Related Art
In most cases, semiconductor memory devices include internal voltage generators. An internal voltage generator receives an external voltage externally applied thereto and generates an internal voltage having a level lower than the external voltage. The internal voltage generated in the internal generator is used as the power voltage of a memory cell array in order to reduce power consumption, obtain high noise immunity, and insure stable operational properties.
FIG. 1
is a circuit diagram of a conventional internal voltage generator. Referring to
FIG. 1
, the conventional internal voltage generator includes a PMOS driving transistor P
11
, a comparator
11
, an OR gate
13
, a PMOS transistor P
12
, and NMOS transistors N
11
and N
12
.
The OR gate
13
receives input signals VCCAP
1
and VCCAP
2
and generates a predetermined control signal VCCAE, which is a pulse type signal. The input signals VCCAP
1
and VCCAP
2
of the OR gate
13
are pulse signals that are generated in response to a signal activated during an active period of a semiconductor memory device.
If the NMOS transistor N
11
is turned on when the predetermined control signal VCCAE is logic “high”, the comparator
11
becomes active. When the input signal VCCAP
2
of the OR gate
13
is logic “low”, the comparator
11
compares an internal voltage VCCA fed back to the comparator
11
via the PMOS transistor P
12
with a predetermined reference voltage VREF and generates a driving signal DR depending on the results. When the input signal VCCAP
2
of the OR gate
13
is logic “high”, the comparator
11
compares a voltage input via the NMOS transistor N
12
with the reference voltage VREF and generates the driving signal DR depending on the results.
An external voltage VDD is applied to the source of the PMOS driving transistor P
11
, and the driving signal DR is applied to the gate of the PMOS driving transistor P
11
. The internal voltage VCCA is output from the drain of the PMOS driving transistor P
11
.
The conventional internal voltage generator shown in
FIG. 1
is considerably affected, however, by variations in the external voltage VDD. For example, if the external voltage VDD increases, the gate-to-source voltage of PMOS driving transistor P
11
increases, causing P
11
to supply an excessive amount of electric charge. As a result, power consumption increases and the internal voltage VCCA becomes unstable.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide an internal voltage generator, for a semiconductor memory device, that can uniformly supply a predetermined amount of electric charge and can generate a stable internal voltage.
It is a second object of the present invention to provide an internal voltage generating method, for a semiconductor memory device, that can uniformly supply a predetermined amount of electric charge and can generate a stable internal voltage.
Accordingly, to achieve the first object, there is provided an internal voltage generator according to the present invention including: a PMOS driving transistor having a source to which the external voltage is applied, a gate to which a driving signal is applied, and a drain from which the internal voltage is output; and a driving signal generator that generates the driving signal. Here, the driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level during variations in the external voltage.
The internal voltage generator according to the present invention may further include a pull-up device that is connected to the gate of the PMOS driving transistor and pulls up the gate of the PMOS driving transistor.
According to a preferred embodiment of the present invention, the driving signal generator includes: a voltage divider that divides the internal voltage in response to a buffered control signal so as to generate a control voltage that is substantially uniform; and an inverter that uses the external voltage as a power voltage, inverts the buffered control signal in response to the control voltage, and outputs the driving signal.
To achieve the second object, there is provided an internal voltage generating method for a semiconductor memory device that generates an internal voltage having a level lower than an external voltage, the method including: generating a control voltage that is substantially uniform by dividing the internal voltage in response to a control signal; generating a driving signal by inverting the control signal in response to the uniform control voltage using the external voltage as a power voltage; and generating the internal voltage in response to the driving signal using the external voltage as a source.


REFERENCES:
patent: 5367491 (1994-11-01), Han et al.
patent: 5747974 (1998-05-01), Jeon
patent: 6046624 (2000-04-01), Nam et al.
patent: 6150860 (2000-11-01), Chun
patent: 6407538 (2002-06-01), Kinoshita et al.
patent: 6459329 (2002-10-01), Kobayashi et al.

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