Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2001-08-07

2003-02-18

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S597000, C438S454000

Reexamination Certificate

active

06521527

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device which can improve element characteristics by a nitrogen implantation technique, and a method of fabricating the same.
2. Description of the Background Art
In general, it is known that source/drain regions of a MOS transistor are formed with shallow junction planes in order to suppress a short channel effect of the MOS transistor. In order to suppress a short channel effect of a P-channel MOS transistor (hereinafter referred to as “PMOS transistor”), it is effective to employ an electrode which is doped in a P type as an electrode material for the PMOS transistor. In order to suppress a short channel effect of an N-channel MOS transistor (hereinafter referred to as “NMOS transistor”), on the other hand, it is effective to employ an electrode which is doped in an N type as an electrode material for the NMOS transistor. A dual gate CMOS transistor is proposed in relation to application of these effects to a CMOS (complementary MOS) transistor which is formed by NMOS and PMOS transistors. In such a dual gate CMOS transistor, a gate electrode which is doped in an N type is employed for the NMOS transistor, while a gate electrode which is doped in a P type is employed for the PMOS transistor.
Conventional methods of forming source/drain regions of PMOS transistors with shallow junction planes are now described.
FIG. 145
is a sectional view for illustrating a first conventional method of forming source/drain regions of a PMOS transistor with shallow junction planes, and
FIGS. 146A and 146B
are sectional views for illustrating a second method. Referring to
FIG. 145
, element isolation oxide film
7
, a gate oxide film
2
, a gate electrode
3
, an oxide film
4
and side wall oxide films
5
are formed on a main surface of an N-type silicon substrate
1
through an ordinary process in the first method. Thereafter the element isolation oxide film
7
, the oxide film
4
and the side wall oxide films
5
are employed as masks to ion-implant boron fluoride ions (BF
2
+
) having a larger mass number than boron ions (B
+
) into the N-type silicon substrate
1
. Thus, source/drain regions
6
are formed with shallow junction planes.
In the second method, element isolation oxide film
7
, an oxide film
4
and side wall oxide films
5
are employed as masks to implant silicon ions (Si
+
) or germanium ions (Ge
+
) into an N-type silicon substrate
1
, as shown in FIG.
146
A. Thus, ion-implanted regions of the N-type silicon substrate
1
are brought into amorphous states. Thereafter boron ions (B
+
) are implanted into the N-type silicon substrate
1
, as shown in FIG.
146
B. Thus, source/drain regions
6
are formed with shallow junction planes. In the second method, the silicon ions or germanium ions are implanted in order to prevent a channeling phenomenon of the boron ions.
When the source/drain regions
6
are formed with shallow junction planes, however, the source/drain regions
6
are disadvantageously increased in sheet resistance. To this end, generally proposed is a countermeasure of providing titanium silicide films
8
having low resistance on surfaces of the source/drain regions
6
, as shown in FIG.
147
.
FIG. 148
is a sectional view showing an exemplary conventional dual gate CMOS transistor. Referring to
FIG. 148
, an N well
13
and a P well
14
are adjacently formed on a main surface of a P-type silicon substrate
11
. Further, element isolation oxide film
12
are formed on the main surface of the P-type silicon substrate
11
at prescribed spaces. P-type source/drain regions
21
are formed on a main surface of the N well
13
at a prescribed space, to hold a channel region
10
therebetween. A gate electrode of a polycide gate structure formed by a polysilicon film
16
which is doped in a P type and a tungsten silicide film
18
which is formed on the polysilicon film
16
is provided on the channel region
10
, through a gate oxide film
15
. An oxide film
19
is formed on the tungsten silicide film
18
. Side wall oxide films
20
are formed on side surfaces of the polysilicon film
16
and the tungsten silicide film
18
.
On the other hand, N-type source/drain regions
22
are formed on a main surface of the P well
14
at a prescribed space, to hold a channel region
10
therebetween. A gate electrode of a polycide gate structure formed by a polysilicon film
17
which is doped in an N type and a tungsten silicide film
18
is provided on the channel region
10
in the P well
14
, through a gate oxide film
15
. An oxide film
19
is formed on the tungsten silicide film
18
, while side wall oxide films
20
are formed on side surfaces of the polysilicon film
17
and the tungsten silicide film
18
.
FIGS. 149
to
157
are sectional views for illustrating a fabrication process for the conventional dual gate CMOS transistor shown in FIG.
148
. With reference to
FIGS. 149
to
157
, the fabrication process for the dual gate CMOS transistor shown in
FIG. 148
is now described.
First, element isolation oxide film
12
are formed on a main surface of a P-type silicon substrate
11
, as shown in FIG.
149
. Further, an N well
13
serving as a PMOS transistor forming region and a P well
14
serving as an NMOS transistor forming region are formed on the main surface of the P-type silicon substrate
11
, to be adjacent to each other.
Then, an oxide film
15
a
is formed to cover the N well
13
and the P well
14
, as shown in
FIG. 150. A
polysilicon film
9
is formed on the oxide film
15
a
and the element isolation oxide film
12
by CVD, and a tungsten silicide film
18
a
is formed on the polysilicon film
9
by sputtering.
Then, the PMOS transistor forming region is covered with a resist film
25
, as shown in FIG.
151
. The resist film
25
is employed as a mask to implant arsenic ions (As
+
) into a portion of the polysilicon film
9
located on the NMOS transistor forming region. Thereafter the resist film
25
is removed.
Then, the NMOS transistor forming region is covered with a resist film
26
as shown in
FIG. 152
, and this resist film
26
is employed as a mask to implant boron fluoride ions (BF
2
+
) into a portion of the polysilicon film
9
located on the PMOS transistor forming region. Thereafter the resist film
26
is removed. An oxide film is formed by CVD, and thereafter this oxide film, the tungsten silicide film
18
a
and the polysilicon film
9
are patterned in the form of gate electrodes by photolithography and anisotropic etching. Thus, the oxide films
19
, the tungsten silicide films
18
and polysilicon films
16
a
and
17
a
are formed as shown in FIG.
153
. Thereafter an oxide film is formed on the overall surface by CVD, and this oxide film is etched back. Thus, side wall oxide films
20
are formed on side surfaces of the gate electrodes, as shown in FIG.
154
.
Then, the PMOS transistor forming region is covered with a resist film
27
, as shown in FIG.
155
. This resist film
27
is employed as a mask to implant arsenic ions into the NMOS transistor forming region. Thereafter the resist film
27
is removed.
Then, the NMOS transistor forming region is covered with a resist film
28
as shown in
FIG. 156
, and this resist film
28
is employed as a mask to implant boron fluoride ions into the PMOS transistor forming region. Thereafter the resist film
28
is removed. Heat treatment is carried out for activating the ions as implanted. Thus, a polysilicon film
16
which is doped in an N type, a polysilicon film
17
which is doped in a P type, N
+
-type source/drain regions
22
and P
+
-type source/drain regions
21
are formed as shown in FIG.
157
. Thus, the exemplary conventional dual gate CMOS transistor of a polycide gate structure is completed.
FIG. 158
is a sectional view showing another exemplary conventional dual gate CMOS transistor. Referring to

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