Method of designing layout for integrated circuit

Details Method of designing layout for integrated circuit Method of designing layout for integrated circuit

2001-03-13

2003-02-11

Crane, Sara (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06519750

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing integrated circuits (ICs) and more particularly, to a method of designing the layout for ICs using a Computer-Aided Designing (CAD) system or tool, which makes it possible to route the signal lines without their re-routing process.
2. Description of the Related Art
Conventionally, well-known Application Specific Integrated Circuits (ASICs) termed Gate Arrays, Standard Cells, and so on have been designed using a CAD tool, in which the Clock Tree Synthesis (CTS) process has become to play an important role. The CTS process is a process to control the propagation delay of a clock signal by assigning a clock driver (i.e., buffer) to each cell array to thereby adjust the delay with the extra capacitance and resistance added by the driver.
With the CTS process, the clock lines for the respective blocks or cells are synthesized in the form of a tree and then, buffers having high driving capability are assigned to the respective branches of the clock line tree. Thus, the relative skew (i.e., the phase difference) of the propagated clock signal among the blocks and/or cells are suppressed, in other words, the clock skew is reduced.
The CTS process is well known and therefore, no further explanation will be needed. However, an example of the documents explaining this process is as follows:
The user's manual (provisional) of the CAD tool, CB-C9 family, VX/VM type, for 0.35 &mgr;tm CMOS cell-based ICs, Design section, published by NEC corporation in 1997.
An example of a prior-art method of designing the layout for ICs using a CAD tool will be explained below with reference to
FIGS. 1
to
6
.
FIG. 1
shows the layout section of a CAD tool for conducting the prior-art method. The layout section of
FIG. 1
comprises a cell information library
101
, a timing restriction information storage
102
, a placement and routing information storage
103
, a functional block placement section
104
, a power and ground line routing section
105
, a cell placement section
106
, a clock line routing section
107
, a signal line routing section
108
, and a clock and signal line re-routing section
109
.
The cell information library
101
stores the cell information for defining the primitive cells. Each of the primitive cells has one of the minimum functions (e.g., a NAND or NOR circuit, an inverter, a buffer, and a flip-flop) that have been prepared to design cell-based ICs. Also, the library
101
stores the wiring layer information for defining the extending direction of the respective wiring layers in the primitive cells.
The cell information in the library
101
is read out and sent to the functional block placement section
104
and the cell placement section
106
as necessary. Also, the cell information and the wiring layer information in the library
101
is read out and sent to the power and ground line routing section
105
, the clock line routing section
107
, the signal line routing section
108
, and the clock and signal line re-routing section
109
as necessary.
The timing restriction information storage
102
stores the timing restriction information about the temporal restriction in signal transmission among the logic elements (i.e., about the timing restriction of the signals other than the clock signal). The timing restriction information in the storage
102
is read out and sent to the cell placement section
106
and the signal line routing section
108
as necessary.
The placement and routing information storage
103
stores the placement information of the primitive cells in the form of net list and the routing information of the wiring lines among the primitive cells. The placement information and the routing information is read out and sent to the functional block placement section
104
, the power and ground line routing section
105
, the cell placement section
106
, the clock line routing section
107
, the signal line routing section
108
, and the clock and signal line re-routing section
109
as necessary.
The functional block placement section
104
determines the functional blocks (i.e., the areas where the primitive cells are functionally separated and laid out), forming a floor plan. This operation is performed on the basis of the cell information from the library
101
and the placement and routing information from the storage
103
. Then, the section
104
supplies the result of the placement (i.e., the floor plan) to the power and ground line routing section
105
.
The power and ground line routing section
105
conducts the routing operation of the power supply lines and the ground lines on the basis of the cell information from the library
101
and the routing information of the wiring layers from the storage
103
. Then, the section
105
supplies the result of the routing operation to the cell placement section
106
.
The cell placement section
106
determines the layout of the primitive cells for each functional block on the basis of the cell information from the library
101
, the placement and routing information from the storage
103
, and the timing restriction information from the storage
102
. Then, the section
106
supplies the result of the layout operation to the clock line routing section
107
.
The clock line routing section
107
conducts the CTS process on the basis of the cell information from the library
101
and the placement and routing information from the storage
103
, thereby determining the routing of the clock lines for each primitive cell. Then, the section
107
supplies the result of the clock line routing operation to the signal line routing section
108
.
The signal line routing section
108
conducts the routing operation of the signal lines for each primitive cell on the basis of the cell information from the library
101
, the placement and routing information from the storage
103
, and the timing restriction information from the storage
102
. Then, the section
108
supplies the result of the signal line routing operation to the clock and signal line re-routing section
109
.
The clock and signal line re-routing section
109
searches the result of the signal line routing operation thus sent and extracts the short-circuited ones therefrom. Then, the section
109
conducts the re-routing operation (i.e., amends the existing layout) of the short-circuited signal lines and the relating clock lines to eliminate the short-circuited ones on the basis of the cell information from the library
101
, the placement and routing information from the storage
103
, and the timing restriction information from the storage
102
. Thus, the section
109
generates the final result of the layout operation and outputs it as the final layout information.
FIG. 2
shows a prior-art layout method conducted with the layout system shown in FIG.
1
.
First, in the step S
101
, the functional block placement section
104
places the functional blocks including the primitive cells to form a floor plan on the basis of the cell information from the library
101
and the placement and routing information from the storage
103
.
In the next step S
102
, the power and ground line routing section
105
determines the routes of the power lines and the ground lines on the basis of the cell information and the wiring layer information from the library
101
.
In the next step S
103
, the cell placement section
106
places the primitive cells in each of the functional blocks on the basis of the cell information from the library
101
, the placement and routing information from the storage
103
, and the timing restriction information from the storage
102
. In this process, the primitive cells are laid out at the specific positions where the timing of the ordinary signals other than the clock signal is judged optimum. If the timing restriction information is not satisfied after a layout of the primitive cells is completed, this layout is amended. This amendment process of the layout is repeated until the restriction information is satisfied

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