Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2000-04-19
2003-11-25
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C327S175000, C327S116000, C327S269000
Reexamination Certificate
active
06654900
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to clock circuits and more particularly to method and apparatus for producing multiple clock signals and controlling the duty cycle of the multiple clock signals.
BACKGROUND OF THE INVENTION
Clock signals are used in a variety of data processing applications to ensure proper processing of data. Typically, a reference clock signal will be received or generated which multiple other clock signals are produced. The reference clock signal may be multiplied up to a higher frequency or divided down to a lower frequency. A combination of multiplying and dividing clock signals allows for many multiples of the referenced clock to be generated (integer or real multiplication).
A phase lock loop (PLL) or a “one shot” circuit may be used to generate a high frequency clock from the referenced clock signal. This is done in many applications to generate a higher frequency clock or to generate a clock frequency that is not an integer multiplication (or division) of the referenced clock frequency. For example, a 22.05 megahertz clock signal may be generated from a 24 megahertz clock signal by using frequency dividers and a phase lock loop. In particular, the 24 megahertz clock signal may be divided by 40, to generate a 600 kilohertz clock signal, which is then multiplied by 147 via a phase lock loop producing a clock having a rate of 88.2 megahertz. The 88.2 megahertz clock signal is then divided by 4 to produce a clock signal of 22.05 megahertz. The result is a real frequency multiplication of the 24 megahertz reference clock by 0.91875.
In many applications, the resulting clock signal is used to trigger transference of data from one data processing circuit to another. The data may be transferred on the rising edge of the clock signal or the falling edge of the clock signal. Thus, when designing a clock for such data transference the accuracy of the clock rate was a primary factor and maintaining a duty cycle of 50% was a distant secondary concern. However, in more recent data processing circuits, data is processed on the rising and falling edges often referred to double edge processing, which is done to improve processing speed, reduce power and reduced die size. For example, as the manufacturing process technology of integrated circuits improve, transistor speeds are increasing, which are allowing processors to complete instructions in a single clock phase as oppose to many cycles. This allows for more instructions to be processed using less circuitry, which reduces both power consumption and die size. However, for double-edged data processing, the data clock is required to have a duty cycle of 50%.
As is known, a 50% duty cycle allows an equal amount of time for processing data on the rising edge as for processing data on the falling edge. If the duty cycle of the clock is not approximately 50%, such as the case of a 60%-40% duty cycle, the processing system would be required to operate at the minimum cycle time set by the 40% duty cycle. For example, if the system is operating with a 24 megahertz clock, the half period of a 50% duty cycle is 20.83 nanoseconds. However, if the minimum half cycle is constrained by a 40%-60% duty cycle clock, the minimum half cycle period is 16.67 nanoseconds, which would be the maximum time for the processor to process an instruction. This is a 4.16 nanosecond reduction of processing time when compared to a 50% duty cycle. With current processing speeds, a reduction of 4.1 nanoseconds is a significant loss of processing power (measured in MIPs).
Typically, a 50% duty cycle system clock is generated from the referenced clock using a multiplying circuit, such as a PLL. It is well known that an analog PLL consumes a great amount of die area and consumes a reasonable amount of power. For large multiplication factors, an analog PLL is an acceptable method. However, for lower frequency multiplication factors, such as multiplying by two or four, the analog PLL is not a good design choice.
A one-shot circuit produces an output pulse that is based on the rising and falling edges of the referenced clock. In effect, a one-shot multiplies the referenced signal frequency by 2. A simple one-shot circuit comprises two input exclusive OR gates (XOR) and some delay elements (usually an even number of inverters). The one-shot is built by directly connecting one of the two XOR inputs to the referenced clock signal. The other XOR input is connected to the delay chain, and is therefore receiving a delayed version of the referenced clock. The one-shot circuit output will pulse high on the rising edge and falling edge of the referenced clock signal. The high pulse will only be as wide as the delay of the delay chain. As such, the one-shot circuit multiplies the referenced clock signal by 2 and does not consume as much power, or area, as an analog PLL. However, the one-shot circuit does not produce a reliable 50% duty cycle because the delay chain is highly sensitive to process variation, temperature variation, and power supply variation.
In addition, a one-shot circuit, due to these sensitivities, is difficult to utilize in a multiple clock environment where the phase differences between clocks of the same rate are to be controlled. Therefore, a need exists for a method and apparatus that provides the simplicity of a one-shot clock multiplication circuit with a control duty cycle of an analog PLL for producing multiple clock signals having a control phase relationship.
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Chang Eric
Lee Thomas
Markison Timothy W.
Sigmatel, Inc.
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