Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-16
2003-10-07
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S388000, C257S900000
Reexamination Certificate
active
06630721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to fabricating a MOSFET transistor having a polysilicon gate conductor with silicide formed simultaneously on top and sidewall surfaces of the gate conductor and on junction regions adjacent to the gate conductor without shorting the conductor to adjacent junctions or consuming the shallow junction regions.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. Generally a dielectric material is formed upon a substrate, such as a monocrystalline silicon wafer. The gate conductor material is then formed upon the dielectric and subsequently patterned to expose the dielectric material deposited upon predetermined impurity regions residing in the semiconductor substrate. Patterning the gate conductor typically involves lithography in which a protective mask, photoresist, has been exposed to light and removed in the areas over the impurity regions prior to an etch process. Ion implantation may then be performed to form lightly doped drain (“LDD”) and source/drain (“S/D”) junctions in the impurity regions. Rapid thermal annealing is typically utilized to complete the formation of the LDD and source/drain junctions. After the impurity regions have been placed into a semiconductor substrate and gate regions defined upon the substrate, an interlevel dielectric may be formed across the topography to isolate the gate regions and the impurity regions. Processing steps may then be performed to create ohmic contacts which connect the gates and/or junctions to other devices in the integrated circuit.
Integrated circuits often employ active devices known as transistors. A transistor includes a pair of impurity regions, or junctions, spaced laterally apart by a gate conductor. The gate conductor is dielectrically spaced above a semiconductor substrate within which the junctions reside. The junctions contain dopants which are opposite in type to the dopants residing within a channel region of the substrate interposed between the junctions. The gate conductor typically comprises polycrystalline silicon (“polysilicon”) which is rendered conductive by implanting dopants therein. Polysilicon can withstand relatively high temperatures. Therefore, a polysilicon gate conductor may be formed prior to performing high-temperature anneal steps, such as the post-implant anneal of the junctions. As such, the gate conductor may be patterned before the source and drain junctions are formed and annealed. In fact, the gate conductor is commonly used as a channel region mask during the formation of the source and drain junctions.
One of the disadvantages of using polysilicon as the gate conductor material, however, is that it inherently has a significantly higher resistivity than metals, such as aluminum. Therefore, the propagation delay of an integrated circuit employing a polysilicon gate conductor may be longer than desired. Consequently, the operational frequency that may be achieved by a circuit employing a polysilicon gate conductor may be somewhat limited. However, forming silicide upon a polysilicon gate conductor helps lower the sheet resistance of the gate conductor. Silicide formed upon polysilicon is generally referred to as polycide. A salicidation process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. Therefore, dielectric sidewall spacers, formed on the sidewalls of a gate conductor prior to salicidation, prevent refractory metal from contacting, and hence reacting with, the sidewalls of the gate conductor. Absent the sidewall spacers, silicide may form upon the sidewall surfaces of the silicon-based gate conductors and undesirably short the gate conductors to adjacent junctions. The resulting silicide is, therefore, self-aligned to regions of high concentrations of silicon and is generally referred to as salicide. In this manner, salicides may be formed simultaneously upon the junctions and the top surface of the polysilicon gate conductors.
FIG. 1
depicts a transistor
10
having salicides formed simultaneously upon the junctions and the top surface of the polysilicon gate conductor. A polysilicon gate conductor
12
is spaced above a semiconductor substrate
14
by a gate dielectric
16
. LDD regions
18
in the semiconductor substrate
14
extend laterally from opposed sidewalls
20
of the polysilicon gate conductor
12
. The polysilicon gate conductor
12
is laterally surrounded by dielectric sidewall spacers
22
formed on opposed sidewalls
20
of the polysilicon gate conductor
12
. The top of the polysilicon gate conductor
24
and the top of the junction regions
26
have been converted to silicide
28
. Source/drain regions
30
in the semiconductor substrate
14
are spaced from the polysilicon gate conductor
12
by a width of the dielectric sidewall spacers
22
.
As the dimensions of modern transistors shrink to accommodate the high demand for faster, more complex integrated circuits, the width of the transistor gates must also shrink. Consequently, a smaller surface area of the polysilicon gate conductor may be exposed to salicidation. Since silicide that is formed on the polysilicon gate conductor reduces the overall gate resistance, a greater thickness of the polysilicon may be converted to silicide to obtain an acceptable resistivity. Unfortunately, the thickness of polysilicon that may be converted to salicide is limited in conventional salicidation processing in which silicides are formed simultaneously on the gate conductor and the junctions of the transistor. As the dimensions of the transistors shrink, in addition to the width of the gate conductor, the depth of the source/drain junctions decreases. If a salicide process completely consumes a relatively shallow junction and penetrates into the substrate underneath the junction, a phenomenon known as “junction spiking” may occur. Junction spiking may undesirably cause the junction to exhibit large current leakage or cause the circuit to electrically short. Therefore, in order to prevent excessive consumption of shallow junctions, the thickness of the salicide formed on the junctions must be limited. Consequently, gate salicides formed simultaneously with junction salicides must also be of limited thickness.
Another disadvantage of polycide gate conductors is geometry-dependent resistivity. As the width of transistor gates is reduced, polysilicon gate conductors exhibit undesirable increases in resistivity. It has been theorized that regions of high resistivity polysilicon, in which mobile carriers become easily trapped, exist in the vicinity of the grain boundaries characteristic of polysilicon films. As these regions become comparable in size to the overall length of the polysilicon gate conductor, insufficient quantities of silicon may be available for the formation of high quality suicides. When such a condition occurs, the formation rate and quality of silicides formed on the upper surface of short-length polysilicon gate conductors may drop below the formation rate and quality of suicides formed on wider polysilicon structures. The increased resistivity exhibited by short-length gate conductor polycides results in an increased gate contact resistance, which reduces the speed of the transistor. Furthermore, geometry-dependent silicide resistivity is undesirable because semiconductor devices and processes are almost universally designed and simulated under the assumption that silicide resistivity will not exhibit a geometric dependence.
Accordingly, it would be advantageous to develop a salicidation process in which a larger portion of the polysilicon gate could be converted to silicide without shorting the conductors to adjacent junctions or consuming shallow source/drain junctions.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a transistor having silicide structures o
Advanced Micro Devices , Inc.
Eckert George
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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