Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-07-13
2003-11-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06650577
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated semiconductor memory having memory cells respectively disposed in a plurality of memory cell arrays. The memory cell arrays are disposed on a semiconductor chip in respective levels running above one another. The invention also relates to a method for repairing such a memory.
In order to repair faulty memory cells in a memory cell array, integrated semiconductor memories, such as DRAM memories, generally have redundant units of memory cells which are able to replace normal units of memory cells containing faulty memory cells, by addressing. The memory cells are usually combined in the memory cell array to form units of individual or a plurality of row lines and column lines, and of redundant row lines and redundant column lines.
The integrated memory is tested by using an external test device, for example, and the redundant elements are then programmed. In that case, a redundancy circuit has programmable elements, e.g. in the form of laser fuses or electrically programmable fuses, which are used for storing the address of a unit to be replaced. They are usually disposed in “fuse banks” and are programmed by using a laser beam or a “burning voltage”, for example in the course of the manufacturing process after the memory has been tested. When the memory is operating, in the course of a memory access operation, the normal units to be replaced are replaced by the appropriate redundant units by addressing, using an appropriate redundancy circuit.
An “MRAM” memory containing memory cells with a magnetoresistive memory effect is known from International Publication No. WO 99/14760, corresponding to U.S. application Ser. No. 09/528,159, filed Mar. 17, 2000. The memory cells have ferromagnetic layers with a state which can be altered in order to store data signals. The memory cells are respectively connected between one of the row lines and one of the column lines and are electrically connected to the respective column line and row line. In that case, the memory cells with a magnetoresistive memory effect have a higher impedance than the row lines and column lines. The column lines are connected to a sense amplifier in order to read a data signal from a selected memory cell.
Since such an MRAM memory contains no selection transistors connecting the memory cells to the respective column line on the basis of the addressing for the purpose of reading or writing a data signal, particular advantages are obtained for the geometric configuration of the memory cells. Thus, the memory cells can be placed in different memory cell arrays disposed on the semiconductor chip in respective levels running above one another. Such a stacked configuration of the memory cell arrays allows a considerable space saving to be achieved.
If the memory repair technology known for DRAM memories is used on such an MRAM memory, then each of the individual memory cell arrays generally needs to be provided with a redundancy circuit containing fuse banks for replacing memory cells in the relevant memory cell array.
Programmable elements such as laser fuses generally cannot be provided in a stacked configuration for accessibility reasons. That means that, with a relatively high number of redundant units of memory cells for the individual memory cell arrays, a memory containing fuse banks disposed next to one another generally requires a relatively large amount of space which in some cases can once again eliminate the space saving accomplished by the stacked memory cell arrays.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor memory having memory cells in a plurality of memory cell arrays and a method for repairing such a memory, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type, in which normal memory cells and redundant memory cells are provided and in which a comparatively space-saving circuit configuration for programming the redundant memory cells for repairing the memory is made possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory, comprising memory cells disposed in a plurality of memory cell arrays and a semiconductor chip on which the memory cell arrays are disposed in levels extended above one another. The memory cells include a plurality of memory cells combined to form normal units of memory cells. The memory cells include a plurality of memory cells combined to form redundant units of memory cells each for replacing a respective one of the normal units. The normal units and the redundant units each have memory cells of the memory cell arrays in a plurality of the levels.
With the objects of the invention in view, there is also provided a method for repairing an integrated semiconductor memory, which comprises testing the memory cells in the memory cell arrays for freedom from fault. Memory cells detected as faulty are replaced with redundant memory cells. A respective normal unit containing a memory cell detected as faulty is replaced with one of the redundant units, upon detecting at least one faulty memory cell.
The invention can be applied to any integrated semiconductor memories which have a plurality of memory cell arrays in respective levels running above one another. Such a configuration can be used, in particular, in MRAM memories. In particular, such a memory has memory cells with a magnetoresistive memory effect which are respectively connected between one of a plurality of column lines and one of a plurality of row lines of the respective memory cell array.
Combining memory cells into normal units and redundant units respectively including memory cells in a plurality of levels makes it possible to reduce the number of programmable elements required for programming overall. By way of example, it is not necessary to provide a dedicated fuse bank for a respective memory cell array. For example, the normal units and redundant units respectively include memory cells from four memory cell arrays disposed above one another. In this case, the number of fuse banks to be provided can be reduced by a factor of four, since a redundant unit includes memory cells not just from one memory cell array but rather from four memory cell arrays. If one of the normal units in this case has at least one faulty memory cell, the relevant normal unit is replaced by one of the redundant units. Therefore, in the example, memory cells in all four memory cell arrays are replaced together by one redundant unit.
In this context, the invention uses the realization that, for example in the case of an MRAM memory having memory cell arrays which are in a stacked configuration, common faults can be expected particularly in the case of memory cells situated above one another. That is to say that, if a memory cell in a memory cell array is faulty, then there is a particular statistical probability of expectation that the memory cell situated below it or above it is likewise faulty. Such statistical probability can be used to define particular units of memory cells in which relatively frequent fault couplings can be observed. According to the invention, such normal units are repaired jointly by one redundant unit.
In a faulty memory cell array in which the memory cells are each connected to a row line and to a column line, when multiple operating faults arise, significant large numbers of the operating faults can usually be detected along column lines or row lines. Thus, by way of example, in the case of a faulty sense amplifier, the operability of the column line connected to that sense amplifier is affected, and therefore all of the memory cells connected thereto. Similar effects of fault couplings can also be observed in three-dimensional configurations of memory cell arrays. Thus, in particular, manufacture-related effects are conceivable which jointly affect memory cells situated above one another in particular (e.g.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Tan T.
Stemer Werner H.
LandOfFree
Integrated semiconductor memory having memory cells in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated semiconductor memory having memory cells in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated semiconductor memory having memory cells in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3171961