Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-07
2003-10-21
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06637013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to Computer Aided Design (CAD) tools. More particularly, the present invention relates to a method and system for automating design rule check error corrections in a CAD environment.
2. Background Art
Computer aided design tools are utilized on a wide scale in many research and development environments to design electrical, mechanical, chemical and/or other types of products. In the field of semiconductor design, such CAD tools help designers implement complex circuit architectures into semiconductor products. Such CAD tools are used for system level design, custom integrated circuit design tools, deep submicron design, logic design and verification, printed circuit board (PCB), package and interconnect design. A popular set of CAD tools, referred to as the Opus CAD design environment, is commercially available from Cadence Design Systems, Inc. of San Jose, Calif. In the Opus CAD design environment, the physical design of an integrated circuit depends on a set of design rules. The design rules are often determined inherently from the type of semiconductor fabrication technology, e.g., CMOS, NMOS, PMOS, etc. which is being utilized to implement the integrated circuit. Design rules typically define physical parameters and relationships such as minimum area, diagonal width, diagonal space, etc., of a physical entity in an integrated circuit. Throughout the development and design of an integrated circuit, such design rules are referenced directly and indirectly by both commercial CAD design tools and custom design tools developed in-house by the designers. Such custom design tools may be used to create designs, check designs for rule violations, or to preprocess or post process a design to or from other design tools. A subset of all of the design rules in the Opus CAD design environment is stored in an internal file referred to as a technical file or “Tech” file. The Tech file is used internally by the Opus CAD tool products.
In an Opus CAD design environment, custom designed CAD tools may be written in the SKILL programming language. The SKILL programming language is a high level language with primitives and operators specifically designed for CAD related tasks and well known to those of ordinary skill in the art. Both commercial and custom-designed CAD programs may be written in the SKILL programming language and are designed to perform specific tasks to assist with the design of an integrated circuit. Specifically, a SKILL program may be used to find the areas that have not been covered by a specific metal. Then it fills those areas with the specific metal according to the design rule. Finally, it finds all the intersecting areas among the filled metal and the consecutive grounded metals. Using metal
2
as an example, it first finds the areas that have not been covered by metal
2
. Then it fills metal
2
in those areas according to the design rule. Finally, it finds all the intersecting areas among the filled metal
2
and grounded metal
1
and metal
3
, so that the program can drop vias to connect the filled metal
2
to metal
1
ground or metal
3
ground.
DIVA, a design verification utility product commercially available from Cadence Design Systems, Inc., of San Jose, Calif., is commonly used to verify a physical design or derive the result of certain logical operations among geometries on the same or different layers of integrated circuit design. In design flow development, it is very common to write a DIVA rules file to get result geometries from some logical operations on geometries of certain layers. For example, to fill a via
5
one finds all of the cross areas of metal
5
(m
5
) vss and metal
6
(m
6
) vss as possible in the result areas and connects them together by filling these areas. In a simple case as mentioned above to fill via
5
, a SKILL program can be written to run the DIVA utility to find all the cross areas between m
5
vss and m
6
vss, derive those areas to a supplement layer called a “hilite” drawing, and use the SKILL program to fill via
5
in all hilite drawing geometries.
Often, in more complex cases, however, there will be some side effects caused by use of the DIVA utility. For example, if the result contains some Design Rule Check (DRC) errors, such errors must be fixed before the flow of the design process continues. Each time the design changes, the design flow has to run once again. Accordingly, it is inconvenient to break the design flow in the middle and have a layout designer fix the DRC errors at that point. Given the large number of designs that need to be run throughout a design flow, a manual fix approach becomes impractical.
Accordingly, a need exists for a technique to automate design rule check error corrections in a CAD environment.
A further need exists for a technique to automate design rule check error corrections in a CAD environment which can be used in an iterative manner until a predetermined level of iterations has been achieved or no more DRC errors are found.
SUMMARY OF THE INVENTION
A technique for automating design rule check (DRC) error corrections in a CAD environment contemplates the use of an automation program to automatically and continuously run a design rule check utility program to generate intermediate results which are processed by the automation program and then supplied back to the design rule check utility program again for execution. The whole process is repeated, in an iterative manner, as many times as needed until a final result is achieved.
In one aspect of the invention, in a computer-aided design environment, a method for eliminating design rule check errors detected by a design verification tool in a set of design data comprises: (a) processing a set of design data with the design verification tool to produce verification results, and attaching a specific property to each type of error detected; (b) determining if the verification results contain an error; (c) if an error is detected in the verification results, modifying the design data in accordance with the attached specific property of the verification results; and (d) repeating steps (a) through (c) sequentially until no errors are found in the verification results or a preset repeat count or time limit has been reached. In one embodiment, if no errors are detected in the verification results the error free design data is processed. In another embodiment, step (a) of processing a set of design data with the design verification tool further comprises: (a.1) creating a design verification tool rules file designed to be able to attach a specific property to each type of error detected and (a.2) processing the design data with the design verification tool using the tool rules file. In another embodiment, step (c) of modifying the design data further comprises augmenting the design data and creating a design verification tool rules file for the augmented design data.
In another aspect of the invention, in a computer-aided design environment, a method for eliminating design rule check errors detected by a design verification tool in a set of design data, including geometric data describing a design, comprises: (a) creating a design verification tool rules file which is designed to be able to attach a specific property to each type of error detected; (b) processing a set of design data with the design verification tool to produce verification results; (c) determining if the verification results contain an error; (d) if an error is detected in the verification results, creating supplemental geometries depending on the attached specific property to resolve a detected error; (e) creating a supplemental design verification tool rules file for the supplemental geometries; and (f) repeating steps (b) through (e) until no errors are found in the design verification results or a preset repeat count or time limit is reached. In one embodiment, if no errors are detected in the verification results then the error free design data is processed.
In another aspect of the inventi
Garbowski Leigh M.
Ritchie David B.
Sun Microsystems Inc.
Thelen Reid & Priest LLP
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