Semiconductor device having triple well structure

Details Semiconductor device having triple well structure Semiconductor device having triple well structure

1997-06-26

1999-08-17

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257269, 257339, 257376, H01L 2976, H01L 2994

Patent

active

059397578

ABSTRACT:
The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.

REFERENCES:
patent: 4600933 (1986-07-01), Richman
patent: 5156989 (1992-10-01), Williams et al.
patent: 5321291 (1994-06-01), Redwine
patent: 5350939 (1994-09-01), Honda et al.
patent: 5548143 (1996-08-01), Lee
patent: 5554883 (1996-09-01), Kuroi
patent: 5739572 (1998-04-01), Noguchi
Patent Abstracts of Japan, Publication No. 06053428 B1 (Feb. 25, 1994).
Patent Abstracts of Japan, Publication No. 06053423 B1 (Feb. 25, 1994).

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