Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-27
2003-10-14
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S349000, C257S350000, C257S354000
Reexamination Certificate
active
06633061
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, and in particular to a SOI substrate having a special multilayer barrier layer, in order to provide a large number of element layers.
SOI (silicon on insulator) substrates have been used as the original material in the field of semiconductor technology for a long time. The advantage of using such SOI substrates is, first, less sensitivity to radiation influences (silicon on sapphire) and the capability to use lower voltages than those which can be used with conventional silicon substrates. Particularly when producing semiconductor circuits with semiconductor elements in different element layers based on a SOI-DRAM, as is described, for example, in U.S. Pat. No. 5,508,219, the use of novel materials often results in problems as a result of the characteristic properties of the semiconductor elements being destroyed or made poorer because of the incompatibility with the semiconductor material of the SOI substrate.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a SOI substrate, an associated production method, and a semiconductor circuit formed in a SOI substrate together with an associated production method which overcome the abovementioned disadvantageous of the prior art apparatus and methods of this general type, and which, in particular, in a simple and cost-effective manner, prevents mutual interference arising from the materials which are used.
With the foregoing and other objects in view there is provided, in accordance with the invention, a SOI substrate, that includes: a first element layer; at least one further element layer; and at least one isolation layer located between the first element layer and the further element layer. The isolation layer includes a diffusion barrier and a multilayer barrier layer with a potential barrier.
In accordance with an added feature of the invention, the multilayer barrier layer includes a plurality of different isolation layers.
In accordance with an additional feature of the invention, the multilayer barrier layer includes an SiO
2
/Si
3
N
4
/SiO
2
layer sequence.
In accordance with another feature of the invention, the multilayer barrier layer includes at least one isolation layer and at least one conductive layer.
In accordance with a further feature of the invention, the multilayer barrier layer includes at least one conductive layer including a material that is selected from the group consisting of Ti, TiSi, Ta, TaN, TiN, Pt, Ru, RuO, Ir, Mo, Co, Ni, Hf, Zr, Ni—Si, MoN, HfN, MoSi, CoSi, TaSi, Au, Ag, Cu, Al, WSiN, C, Fe, W, WN and WSi
x
.
In accordance with a further added feature of the invention, the at least one further element layer includes a layer that is selected from the group consisting of an isolating layer, a semiconductive layer and a conductive layer.
In accordance with a further additional feature of the invention, the multilayer barrier layer includes a thermal compensation layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing a SOI substrate having a plurality of element layers, that includes the following steps: a) forming an element layer and at least one part of a multilayer barrier layer on a first wafer; b) forming a splitting boundary layer and at least a further part of the multilayer barrier layer on at least one second wafer; c) connecting the first wafer and the at least one second wafer to form a common multilayer barrier layer such that the common multilayer barrier layer has a potential barrier and a diffusion barrier; and d) splitting a part of the at least one second wafer at the splitting boundary layer.
In accordance with an added mode of the invention, the method includes steps of: providing the first wafer with a semiconductor substrate; providing the second wafer with a semiconductor substrate; in step a), forming an SiO
2
/Si
3
N
4
/SiO
2
layer sequence as a part of the multilayer barrier layer on the first wafer; and in step b), forming an SiO
2
layer as a part of the multilayer barrier layer on the second wafer.
In accordance with an additional mode of the invention, the method includes steps of: providing the first wafer with an isolating substrate; providing the second wafer with a semiconductor substrate; in step a), forming a conductive layer/SiO
2
layer sequence as a part of the multilayer barrier on the first wafer; and in step b), forming an SiO
2
layer as a part of the multilayer barrier layer on the second wafer.
In accordance with another mode of the invention, the method includes, in step a), forming the multilayer barrier layer with a conductive layer that includes a material selected from the group consisting of Ti, TiSi, Ta, TaN, TiN, Pt, Ru, RuO, Ir, Mo, Co, Ni, Hf, Zr, NiSi, MoN, HfN, MoSi, CoSi, TaSi, Au, Ag, Cu, Al, WSiN, C, Fe, W, WN and WSi
x
.
In accordance with a further mode of the invention, the method includes, in step c), using a wafer bonding method to connect the first wafer and second wafer.
In accordance with a further added mode of the invention, the method includes using a heat treatment to perform the step of splitting the part of the at least second wafer at the splitting boundary layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor circuit, that includes a SOI substrate with: a first element layer, at least one second element layer, and at least one isolation layer located between the first element layer and the second element layer. The isolation layer includes a diffusion barrier and a multilayer barrier layer with a potential barrier. The semiconductor circuit also includes: at least one first semiconductor element that is formed in the first element layer; at least one second semiconductor element that is formed in the at least second element layer; and a conductive diffusion barrier layer electrically connecting the first semiconductor element and the second semiconductor elements.
With the foregoing and other objects in view there is provided, in accordance with the invention, a DRAM memory cell, that includes a SOI substrate with: a first element layer, at least one second element layer, and at least one isolation layer located between the first element layer and the second element layer. The isolation layer includes a diffusion barrier and a multilayer barrier layer with a potential barrier. The DRAM memory cell also includes: at least one first semiconductor element that is formed in the first element layer; at least one second semiconductor element that is formed in the at least second element layer; and a conductive diffusion barrier layer electrically connecting the first semiconductor element and the second semiconductor elements. The first semiconductor element includes a selection transistor; and the second semiconductor element includes a trench capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing a semiconductor circuit in a SOI substrate, that includes providing a SOI substrate that includes: a first element layer, at least one second element layer, and at least one isolation layer located between the first element layer and the second element layer. The isolation layer includes a diffusion barrier and a multilayer barrier layer with a potential barrier. The method also includes steps of: forming a mask layer corresponding to the multilayer barrier layer; using the mask layer to form a deep trench into the second element layer; forming at least one second semiconductor element in the second element layer; forming at least one conductive diffusion barrier layer that prevents diffusion of impurities into the first element layer, the at least one conductive diffusion barrier layer also serving for connection to the at least one second semiconductor element; and forming at least one first semiconductor
Lützen Jörn
Sell Bernhard
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Ngo Ngan V.
Stemer Werner H.
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