Semiconductor devices with reduced control gate dimensions

Details Semiconductor devices with reduced control gate dimensions Semiconductor devices with reduced control gate dimensions

1999-02-04

2003-02-04

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S756000, C438S593000

Reexamination Certificate

active

06515328

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device wherein a multilayered structure is etched to form a pattern therein. The invention is particularly useful in etching a plurality of silicon-based layers at high etch rates and at a high etch rate ratio to an underlying dielectric layer using a chlorine and oxygen etch chemistry.
BACKGROUND ART
The escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
Conventional semiconductor devices comprise a substrate and various structural layers thereon, in which individual circuit components are formed. The formation of various circuit components is partly accomplished by employing conventional photolithographic techniques to form a mask on the substrate and further etching through openings in the photoresist-mask to one or more layers of the substrate. Practically all semiconductor devices incorporate a multitude of such patterning and etching processes.
An exemplary memory cell
8
, of a conventional memory device, is depicted in
FIG. 1A
, viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and a source region
13
a
and a drain region
13
b
formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polycrystalline silicon (polysilicon).
On top of control gate
26
is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a.
When programmed, floating gate
16
will have a binary charge corresponding to either a 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate
16
does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge is removed from floating gate
16
by way of the erasure voltage applied to source
13
a.
FIG. 1B
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG.
1
A). In
FIG. 1B
, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1B
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a portion of floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a
. Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b.
Floating gates
16
a,
16
b,
and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a
and
14
b.
Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a,
16
b,
and
16
c
and field oxides
14
a
and
14
b.
Interpoly dielectric layer
24
isolates floating gates
16
a,
16
b
and
16
c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of
FIGS. 1A and 1B
, place a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells.
Of particular importance in memory devices is the formation and dimensions of the gate electrode. Gate dimensions are critical since the gate electrode controls the flow of electrons and is vital to proper device operation. As described above, a gate electrode is formed by depositing a polysilicon film at a uniform thickness and by subsequent deposition of necessary device layers with further processing steps thereto. The polysilicon layer employed in the control gate is typically deposited at a thickness of about 1500 Å which is greater than the thickness of the corresponding polysilicon layer in the floating gate. The greater thickness of the control gate is necessary to compensate for process limitations in the formation of a memory stack structure.
A semiconductor substrate having a conventional memory stack
10
is shown in FIG.
2
. The memory stack comprises a plurality of layers including a tunnel oxide layer
15
overlying substrate
12
, a first polysilicon layer
16
on tunnel oxide
15
, an ONO layer
24
on polysilicon layer
16
, a second polysilicon layer
26
on ONO layer
24
, and a silicide layer
28
on polysilicon layer
26
. The memory stack also includes a polysilicon cap layer
30
overlying silicide layer
28
and a silicon oxynitride layer
32
on polysilicon cap layer
30
.
FIG. 3
illustrates a flow diagram employing a conventional etch process in the preparation of memory stack
10
of FIG.
2
. The method begins in step
40
, where the multi-layer semiconductor substrate having a silicon oxynitride top layer is covered with a photoresist layer. The photoresist layer is then patterned in step
42
to form a photoresist mask exposing select regions of the underlying silicon oxynitride layer. The semiconductor substrate is then inserted into an oxide etch chamber in step
44
, and an oxide etching operation is performed to etch the exposed regions of the underlying silicon oxynitride layer to expose the underlying poly cap layer. The semiconductor substrate is then moved in step
46
from the oxide etch chamber to a polysilicon etch chamber, where a polysilicon etch process is performed on poly cap layer
30
and silicide layer
28
.
Conventional etch chemistry and equipment requires that a high selectivity to the silicide be achieved so that all of silicide layer
28
can be cleared while the underlying polysilicon layer
26
remains intact. However, achieving a high selectivity is difficult using conventional processes particularly since the silicide and polysilicon layers have similar etching properties. Thus, to ensure the complete etching of silicide layer
28
requires the partial etching of underlying polysilicon
26
. The resulting structure is depicted in
FIG. 4
, where the numerals represent layers as described for
FIG. 2
(the patterned photoresist layer is not shown for illustrative convenience).
Further, should polysilicon underlayer
26

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