Semiconductor device having line-and-space pattern group

Details Semiconductor device having line-and-space pattern group Semiconductor device having line-and-space pattern group

2002-10-22

2003-12-30

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S758000

Reexamination Certificate

active

06670684

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-324144 filed on Oct. 22, 2001; the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a periodic line-and-space pattern group. Particularly, the present invention relates to a semiconductor device in which a periodic line-and-space pattern group is adjacent to a pattern having different periodicity.
The semiconductor device has a plurality of memory transistors. The memory transistors have a plurality of gate wirings. The gate wirings are periodically positioned. It is preferable that widths of the gate wirings are equal, and that intervals between the gate wirings are equal. However, when the gate wirings are regarded as one pattern group, the width and interval of a gate wiring located at an end of the pattern group may differ from the widths and intervals of the rest of the gate wirings.
Therefore, previously, a dummy pattern having the same width and the same interval as the gate wirings of the pattern group has been formed adjacent to the end of the pattern group. All gate wirings of the pattern group were arranged with the same widths and at the same intervals. However, because the dummy pattern is set to a semiconductor memory, a problem is generated in that the area of the semiconductor memory increased.
SUMMARY OF THE INVENTION
A semiconductor device according to embodiments of the present invention includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first pattern group having a plurality of first conductors formed on the first insulting film, respectively, having a first width and separated from each other by a first interval, a second conductor formed separately from a first conductor of the plurality of first conductors at an end of the first pattern group by a first distance in parallel with the plurality of first conductors and having a second width larger than the first width, a third conductor formed on the same side as the second conductor with respect to the first pattern group and separated from the first conductor by the first distance and having a width equal to the second width, and a fourth conductor formed between the second and third conductors and separated from the first conductor by the first distance and having a width equal to the second width.
A semiconductor device according to embodiments of the present invention includes a semiconductor substrate, a first memory cell array having a plurality of first gate wirings in parallel with each other formed on the semiconductor substrate and separated from each other by an interval and respectively having a first width, a first select transistor having a second gate wiring with a second width different from the first width and formed on the semiconductor substrate adjacent to the first memory cell array in parallel with the first gate wirings, a second select transistor having a third gate wiring formed on the semiconductor substrate adjacent to the first memory cell array on the same side as the first select transistor with respect to the first memory cell array on an extension line of the second gate wiring, and a dummy pattern formed adjacent to the first memory cell array between the second gate wiring and the third gate wiring in parallel with the first gate wirings and having a width equal to the second width.


REFERENCES:
patent: 6531357 (2003-03-01), Takeuchi et al.
patent: 2000-164734 (2000-06-01), None

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