Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-09-21
2003-02-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S029000
Reexamination Certificate
active
06525569
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital circuits in general, and in particular to digital driver circuits. Still more particularly, the present invention relates to a digital driver circuit having shapable transition waveforms.
2. Description of the Prior Art
Driver circuits are commonly utilized within electronic circuits for boosting signal strengths from one circuit block to another. Referring now to the drawings and in particular to
FIG. 1
, there is depicted a schematic diagram of a conventional driver circuit. As shown, a driver circuit
10
includes four inverters
11
-
14
connected in series between an input
16
and an output
17
. Each of inverters
11
-
14
is comprised of a p-channel transistor and an n-channel transistor connected in series between a power supply and ground.
In general, the slew rate of a waveform (in up transitions and down transitions) from a conventional driver circuit, such as driver circuit
10
, is completely determined by the device characteristics of the components within the driver circuit. Furthermore, the slew rates vary widely among various driver circuits due to different fabrication processes. However, for a high-speed multi-drop circuit network having a small signal swing, it is very important to have a consistent signal transition shape and a consistent transition slew rate.
Consequently, it is desirable to provide an improved driver circuit that generates a consistent signal transition shape and a consistent transition slew rate independent of the fabrication process.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a driver circuit includes multiple branches of inverter banks connected in parallel. Each of the inverter banks includes an equal number of impedance-controllable inverters connected in series, and a capacitor can be connected between two impedance-controllable inverters within an inverter bank. Each of the impedance-controllable inverter includes an up-level impedance control and a down-level impedance control. The impedance of the p-channel transistors within an impedance-controllable inverter can be adjusted via the up-level impedance control. Similarly, the impedance of the n-channel transistors within the impedance-controllable inverter can be adjusted via the down-level impedance control. Within an inverter bank, the impedance of the impedance-controllable inverters and the capacitance of the capacitors form a set of controlled time constants. By selecting the proper time constants, a desirable up transistor shape and a desirable down transition shape can be obtained for the driver circuit.
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Bracewell & Patterson LLP
Cho James H.
Tokar Michael
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