Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-21
2003-11-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S643000, C438S653000, C438S666000, C438S668000, C438S669000
Reexamination Certificate
active
06649504
ABSTRACT:
The present invention concerns a method for building high aspect ratio electrodes in an electrode means comprising parallel electrodes in a dense arrangement, wherein the method comprises successive process steps for a) depositing a first global layer of electrode material with height h on a substrate, b) patterning the electrode material to form first parallel electrodes of the electrode means, said first electrodes having a width w and height h and being separated by a recess of width d, and wherein the method is characterized by comprising successive further process steps for c) covering the first electrodes with a barrier layer of thickness &dgr;, &dgr; being a fraction of width w, whereby the width d of the recess becomes equal to 2w+2&dgr;, d) depositing a second global layer of electrode material over the first electrodes with the barrier layer and filling the recesses therewith, e) patterning a second layer of electrode material to form second parallel electrodes of the electrode means in the recesses between the electrodes and the barrier layer covering the latter, said second electrodes extending above the first electrodes to a height H−h and being insulated therefrom by means of the barrier layer, whereafter the sequence of process steps c)-e) are alternatingly applied as required to the first and second electrodes respectively until the desired aspect ratio for all electrodes is obtained in a final process step after performing n sequences of the successive process steps c)-e), a final process step comprising applying electrode material to obtain electrodes with approximately equal height and then removing excess electrode material in a planarizing process.
The present invention is related to a method for manufacturing an electrode means as disclosed in the co-pending international patent application No. PCT/NO02/00414 and belonging to the same applicant. This patent application teaches a method for making an electrode means comprising parallel strip-like electrodes in a first and second electrode layers respectively, and contacting a global layer of a functional medium provided therebetween. The electrodes of the second layer are oriented orthogonally to the electrodes of the first layer, forming a matrix of electrodes that is capable of addressing functional elements in the functional medium, said elements being defined as volume element thereof between the respective crossing electrodes of the first and second layer. The parallel strip-like electrodes in each layer are provided in a very dense arrangement, allowing a very high fill factor of electrode material in a given device area. Actually this fill factor can be made close to unity as the parallel strip-like electrodes in a layer will be mutually separated by very thin insulating barrier layer only and this barrier layer has a width that is only a fraction of the width of the parallel strip-like electrodes. Electrode means of this kind are suited for use in matrix-addressable devices, for instance a memory device with a functional medium in the form of a ferroelectric memory material sandwiched between two electrode layers, such that the electrodes of the first electrode layer may form word lines and the electrodes in the second electrode layer bit lines in the electrode means, such that a memory cell can be defined and addressed at the crossing between an electrode of respectively the first and the second electrode layers.
The dense electrode arrangement in electrode means of this kind can e.g. be applied to a memory device of the kind disclosed in the co-pending international patent application PCT/NO02/00390, wherein memory material is not only provided in sandwich, but also additionally applied over the side edges of the addressing electrodes or in recesses provided therein, thus allowing the switching of memory cells not only in the vertical direction, as will be the case with the ferroelectric memory material sandwiched between electrode means, but also in lateral directions such that multidirectionally switchable ferroelectric memory cells are obtained. Similar electrode means with the electrodes in a dense arrangement are also discussed in the co-pending international patent application PCT/NO02/00397 belonging to the same applicant and disclosing a field-effect transistor structure with extremely short channel length.
A method for fabricating dense electrodes are generally disclosed in U.S. Pat. No. 5,017,515 (Gill, assigned to Texas Instruments Inc.). This publication discloses how a dense electrode pattern can be formed as an electrode layer with parallel strip-like electrodes having a width corresponding to a minimum definable feature obtainable in a photolithographic process. Adjacent parallel strip-like electrodes are mutually insulated by a thin barrier of insulating material, and the thickness of this barrier is not constrained by design rules as applicable to photomicrolithographic and etching processes. Every second strip-like electrode is formed in a photolithographic process while the additional electrodes provided between these by providing electrode material over the parallel strip-like electrode structures already in place and filling the recesses therebetween, whereafter a planarization step leaves a single electrode layer of parallel strip-like electrodes with a low aspect ratio and mutually isolated by a thin barrier of insulating material.
In all applications as disclosed by the three above-mentioned co-pending Norwegian patent applications, it will be desirable to employ electrodes with a high aspect ratios, i.e. with a ratio between the electrode height h and the electrode width w as large as possible. In ferroelectric memory applications a high aspect ratio is of great importance when the memory cells are provided in geometrical configurations that shall allow their definition in three dimensions and permit not only a vertical switching direction, but also lateral switching directions. In such cases the memory cell height will be equal or almost equal to the height of the addressing electrodes. In integrated transistor/memory structures with ultrashort channel length the ferroelectric material is provided between the source and drain electrodes of a field-effect transistor provided on e.g. a silicon substrate with appropriately doped regions. The ferroelectric memory material now provides a memory cell that is switchable in lateral directions and which moreover also functions as a gate insulator, as it will not only be present between the source and drain electrodes, but also covers the top surfaces thereof and ensures that the gate electrode is properly insulated from the former. Such a configuration moreover offers the possibility of a three-bit or triple memory cell, as using the electrodes of the transistors for addressing the ferroelectric memory material now shall allow the storage of three separately addressable bits therein, or, as given by a protocol, a three-bit word.
If a switchable or addressable functional material is provided so as to be switched between electrodes in a dense electrode arrangement, the height dimension of the cell is of course important and will be equal to the electrode height. Unfortunately the electrode height does not scale with the electrode density, but as it will be important to improve the signal noise ratio and signal strength in general by increasing the electrode height and thus also the height of a cell of a functional material contacting the electrode at sides thereof, it is desirable to have electrodes with very high aspect ratios.
However, building electrodes with very large aspect ratio, i.e. a high value of h/w is a challenging task in a present-day silicon technology relying on photomicrolithographic processes and etching. If the etching is to take place over an extended area, it will be very difficult to obtain uniform and even side edges, i.e. the side walls of the electrodes formed in the etching process, and there is an inherent danger of undercutting the side edges in the etching process. Generally there will be a
Gurley Lynne A.
Jacobson & Holman PLLC
Niebling John F.
Thin Film Electronics ASA
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