Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-07
2003-11-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06649512
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the fabrication of semiconductor devices, and more particularly to a method for improving adhesion of a low k dielectric to a barrier layer in the damascene process.
2. Description of the Related Art
As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
Copper has disadvantages when compared to aluminum that must be overcome. For example, copper is much more susceptible to oxidation during processing. Copper also tends to diffuse into adjacent materials, including dielectrics. To use copper for interconnections, therefore, it is necessary to encapsulate the copper in barrier materials.
It is common in the art to deposit a barrier of a metal material after the copper layer is deposited, typically called a sealing layer. Typically in the art, this sealing layer (also called a cap layer, or an encapsulation layer) overlying the copper is composed of silicon nitride, though other materials are used.
FIG. 1
is a cross-section showing a dual damascene wiring according to the prior art. A semiconductor substrate
100
and an insulating layer
102
are depicted. Interconnection trenches are formed in the insulating layer
102
, and a copper layer
104
has been deposited overlying the insulating layer
102
and filling the trenches. The excess copper layer
104
is then polished back to the insulating layer
102
by chemical mechanical polishing (CMP). Thereafter, a sealing layer
106
is deposited. A low k dielectric layer
108
having dual damascene structures is formed on the sealing layer
106
.
Also, a copper layer
110
is deposited overlying the low k dielectric layer
108
and filling the dual damascene structures. Herein, the copper layer
110
in the dual damascene structures is connected to the copper interconnect
104
through removal of part of the sealing layer
106
, as shown in FIG.
1
. The excess copper layer
110
is then polished back to the low k dielectric layer
108
by CMP.
This sealing layer
106
, typically silicon nitride (SiN), serves as a metal barrier layer to prevent the copper atoms from the layers
104
,
110
diffusing into insulating layer
102
and the low k dielectric layer
108
. In addition, the sealing layer
106
can be used as an etch stop layer for a dual damascene process.
However, the sealing layer between the low k dielectric and copper interconnects creates reliability problems such as copper line-to-line electronic migration (EM) and time dependent dielectric breakdown (TDDB) between copper lines. For example, after being deposited onto the copper surface, an additional dielectric layer will be deposited over the sealing layer. The deposition of the dielectric layer produces stress, which can crack or break the sealing layer. Moreover, in the subsequent CMP of dual damascene process, poor adhesion between the sealing layer and dielectric layers causes the dielectric layer to peel from the sealing layer. The peeling of the dielectric layer creates a path for copper to diffuse outward and for moisture or other contaminates to diffuse inward.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to perform a plasma treatment on a sealing layer to enhance adhesion between the low k dielectric layer and the sealing layer.
It is another object of the invention to form an adhesion layer between the low k dielectric layer and the sealing layer to prevent sealing layer damage during formation of the low k dielectric layer and peeling of the low k dielectric layer after subsequent CMP.
An aspect of this invention is to provide a method for forming a barrier layer between a low k dielectric and metal interconnects, comprising the steps of: providing a substrate covered by an insulating layer having the metal interconnects; forming a sealing layer on the metal interconnects and the insulating layer; performing a plasma treatment on the sealing layer by a reaction gas including at least one of CO
2
, NH
3
, NO
2
, SiH
4
, trimethylsilane (3MS), and tetramethylsilane (4MS); and forming a low k dielectric layer on the sealing layer. The sealing layer is composed of SiN, SiC, SiCH, SiCO or SiCN.
Another aspect of this invention is to provide a method for forming a barrier layer between a low k dielectric and metal interconnects, comprising the steps of: providing a substrate covered by an insulating layer having the metal interconnects; forming a sealing layer on the metal interconnects and the insulating layer; forming an adhesion layer on the sealing layer; and forming a low k dielectric layer on the adhesion layer. The sealing layer is composed of SiN, SiC, SiCH, SiCO or SiCN. Moreover, the adhesion layer is formed by chemical vapor deposition using a reaction gas including at least one of CO
2
, NH
3
, NO
2
, SiH
4
, 3MS, and 4MS or is formed by coating silicate solution.
REFERENCES:
patent: 6071809 (2000-06-01), Zhao
patent: 6472306 (2002-10-01), Lee et al.
patent: 6509623 (2003-01-01), Zhao
patent: 6569777 (2003-05-01), Hsu et al.
Hsue Chen-Chiu
Lee Shyh-Dar
Hoang Quoc
Merchant & Gould P.C.
Nelms David
Silicon Integrated Systems Corp.
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