Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-13
2003-11-25
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S305000, C257S346000, C257S387000, C257S404000, C257S408000, C257S409000
Reexamination Certificate
active
06653686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to doped semiconductor transistors and more particularly to doped short-channel devices which have channel lengths less than 0.05 &mgr;m and which maintain acceptable threshold voltages, and methods of making such devices.
2. Description of the Related Art
Conventional metal oxide semiconductor field effect transistor (MOSFET) device structures are continuously being reduced in size to increase processing speed and decrease manufacturing cost. Conventional methods of reducing the size of MOSFET devices shrink all the dimensions of the device proportionally.
However, as the channel length in the MOSFET is reduced to increase speed, a “short-channel” effect often occurs which severely degrades the device characteristics. More specifically, the short channel effect is an undesirable increase in the threshold voltage of the gate as the channel length is reduced.
Therefore, there is a conventional need for a method and structure which overcomes the short channel effect and allows MOSFET structures having channel lengths of approximately 0.05 &mgr;m to produce consistent threshold voltages.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for a doping profile for controlling short-channel devices having channel lengths down below 0.05 &mgr;m, and the methods of making such profiles.
More specifically, the invention is a semiconductor device comprising a gate, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer, and gate and drain regions on opposite sides of the halo implant and below the oxide layer. The self-aligned compensation implant reduces a threshold voltage of the semiconductor device and has a doping concentration for controlling a threshold voltage reduction of the semiconductor device that varies depending upon a channel length of the semiconductor device.
The invention also includes method of manufacturing a semiconductor device comprising steps of successively depositing an oxide layer and a dielectric layer on a semiconductor substrate, forming a channel in the oxide layer and the dielectric layer, forming spacers in the channel, implanting an impurity in the semiconductor substrate through the channel to form a self-aligned compensation implant in the semiconductor substrate, depositing an oxide layer in the channel on the semiconductor substrate, filling the channel with a conductive material to form a gate over the oxide layer, removing all of the dielectric layer, removing a portion of the oxide layer such that the oxide layer remains between the gate and the semiconductor substrate, and doping areas of the semiconductor substrate adjacent the gate to form a halo implant and source and drain regions in the semiconductor substrate.
The implanting step further comprises a step of varying a doping concentration of the self-aligned compensation implant for controlling a threshold voltage reduction of the semiconductor device. The step of varying a doping concentration of the self-aligned compensation implant is dependent upon a channel length of the semiconductor device.
The invention also includes a method of manufacturing a semiconductor device comprising steps of successively depositing an oxide layer and a dielectric layer on a semiconductor substrate, forming a channel in the oxide layer and the dielectric layer, depositing an oxide layer in the channel on the semiconductor substrate, partially filling the channel with a conductive material, implanting an impurity in the semiconductor substrate through the conductive material and the oxide layer in the channel to form a self-aligned compensation implant in the semiconductor substrate, completely filling the channel with the conductive material to form a gate over the oxide layer, removing all of the dielectric layer, removing a portion of the oxide layer such that the oxide layer remains between the gate and the semiconductor substrate, and doping areas of the semiconductor substrate adjacent the gate to form a halo implant and source and drain regions in the semiconductor substrate.
Once again, the implanting step further comprises a step of varying a doping concentration of the self-aligned compensation implant for controlling a threshold voltage reduction of the semiconductor device and the step of varying a doping concentration of the self-aligned compensation implant is dependent upon a channel length of the semiconductor device.
The invention also includes a method of manufacturing a semiconductor device comprising steps of forming a sacrificial mask over a gate area of a substrate, forming spacers adjacent the sacrificial mask, forming an opening in the sacrificial mask, implanting an impurity in the semiconductor substrate through the opening in the sacrificial mask to form a self-aligned compensation implant in the semiconductor substrate, removing the sacrificial mask, depositing an oxide layer between the spacers on the semiconductor substrate, forming a gate between the spacers and over the oxide layer, and doping areas of the semiconductor substrate adjacent the gate to form a halo implant and source and drain regions in the semiconductor substrate.
Again, the implanting step further comprises a step of varying a doping concentration of the self-aligned compensation implant the step of varying a doping concentration of the self-aligned compensation implant is dependent upon a channel length of the semiconductor device.
REFERENCES:
patent: 4857141 (1989-08-01), Abe et al.
patent: 5118636 (1992-06-01), Hosaka
patent: 5199994 (1993-04-01), Aoki
patent: 5719430 (1998-02-01), Goto
Cheung, Esq. Wan Yee
International Business Machines - Corporation
McGinn & Gibb PLLC
Wojciechowicz Edward
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