Semiconductor memory device using hemispherical grain...

Details Semiconductor memory device using hemispherical grain... Semiconductor memory device using hemispherical grain...

2000-12-20

2003-02-11

Chaudhuri, Olik (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S303000, C257S306000, C257S309000, C257S905000, C438S255000, C438S398000

Reexamination Certificate

active

06518612

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a semiconductor memory device incorporating textured electrodes for implementing a high-density storage capacitor and a method for the manufacture thereof.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly due to down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, several methods have been proposed such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing a three-dimensionally arranged capacitor is a long and tedious one and consequently incurs high manufacturing costs. Therefore, there is a strong demand for a memory device that can reduce the cell area while securing a requisite volume of information without requiring complex manufacturing steps.
In an attempt to meet the demand, a high-density dynamic random access memory (DRAM) which incorporates bottom electrodes having textured surface morphology has been proposed.
FIG. 1
is a cross sectional view setting forth a conventional high-density semiconductor memory device
100
as disclosed in U.S. Pat. No. 6,015,986, entitled “RUGGED METAL ELECTRODES FOR METAL-INSULATOR-METAL CAPACITORS”. The semiconductor memory device
100
includes an active matrix
10
incorporating metal oxide semiconductor (MOS) transistors therein, with a bottom electrode
25
of a capacitor structure formed on top of the active matrix
10
.
FIGS. 2A
to
2
F illustrate prior art manufacturing steps involved in manufacturing a semiconductor memory device
100
.
As shown in
FIG. 2A
, the process for manufacturing a semiconductor memory device
100
according to the prior art begins with the preparation of an active matrix
10
having a silicon substrate
2
, the MOS transistors formed thereon, an isolation region
4
, a bit line
18
formed between the MOS transistors, a pair of poly plugs
16
, word lines
20
formed on top of the isolation region
4
and a first insulating layer
22
formed on top of the MOS transistors. The insulating layer
22
, e.g., made of boron-phosphor-silicate glass (BPSG), is formed over the entire surface by chemical vapor deposition (CVD). The MOS transistor includes a pair of diffusion regions
6
serving as a source and a drain, a gate oxide
8
, a spacer
14
and a gate line
12
.
In a subsequent step, shown in
FIG. 2B
, a sacrificial layer
24
, which may be made of a material such as phosphosilicate (PSG), is formed on top of the active matrix
10
and patterned into a predetermined configuration, thereby opening top portions of the poly plugs
16
. In an ensuing step, a conductive layer
28
, which may be made of a polysilicon, is formed on top of the patterned sacrificial layer
24
and the active matrix
10
, as shown in FIG.
2
C.
Thereafter, the top-most portions of the conductive layer
28
are removed by a planarizing process such as a chemical mechanical polishing (CMP) or an anisotrophic etching until the sacrificial layer
24
is exposed. Next, the sacrificial layer
24
is removed by using a method such as a wet etching, thereby obtaining electrode structures
25
, as shown in FIG.
2
D.
In a next step, shown in
FIG. 2E
, the electrode structure
25
is subjected to a high vacuum anneal to form hemispherical grained (HSG) polysilicons
26
on surfaces thereof. Rapid thermal processing (RTP) may be used at high vacuum to further promote HSG formation.
One of the major shortcomings of the above-described semiconductor memory device
100
is that it is very possible to form HSG polysilicons bridges between outsides of neighboring electrode structures since the upper HSG polysilicons
32
, formed on top of the electrode structure
25
, are easily detached from the electrode structure
25
. The detached upper HSG polysilicons
32
may fall into a spacing between adjacent electrode structures and short each other.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating a plurality of electrodes provided with rugged side surfaces and a rugged bottom surface, wherein the rugged side surfaces are inclined at a predetermined angle with respect to the rugged bottom surface.
It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating a plurality of electrodes provided with rugged side surfaces and a rugged bottom surface, wherein the rugged side surfaces are inclined at a predetermined angle with respect to the rugged bottom surface.
In accordance with one aspect of the present invention, there is provided a semiconductor device, comprising an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors; and a number of bottom electrodes formed on top of the active matrix with rugged side and bottom surfaces.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising the steps of a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors, and a first insulating layer formed around the conductive plugs; b) forming a sacrificial layer on top of the active matrix and patterning the sacrificial layer into a predetermined configuration, thereby obtaining a patterned sacrificial layer; c) forming spacers on the sides of the patterned sacrificial layer; d) forming a conductive layer on top of the patterned sacrificial layer, the spacers and the active matrix; e) forming a photoresist layer on top of the conductive layer; f) planarizing portions of the photoresist layer and the conductive layer placed on top of the patterned sacrificial layer until the patterned sacrificial layer is exposed, thereby opening portions of the conductive layer; g) carrying out a carbon treatment on the opened conductive layer; h) removing the sacrificial layer and the photoresist layer, thereby obtaining bottom electrode structures; and i) forming hemispherical grained (HSG) polysilicon on side and bottom surfaces of the bottom electrode structures.


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