Partial array self-refresh

Details Partial array self-refresh Partial array self-refresh

2001-11-19

2003-11-18

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000

Reexamination Certificate

active

06650587

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits and in particular to a refresh operation in a memory device.
KACKGROUND OF THE INVENTION
Memory devices such as dynamic random access memory (DRAM) devices are widely used to store data in computers and electronic products.
A typical DRAM device has many memory cells. Each memory cell is capable of storing a bit of data. The value of the data in each memory cell is determined by the value of a charge held by the memory cell. As a known electrical property, charge loses its value over time due to leakage and other factors, causing data to become invalid. Therefore, to retain the validity of the data, the memory cells are periodically refreshed to keep the charges at their original values.
In a typical DRAM device, the memory cells are refreshed during a refresh mode, in which all memory cells are refreshed regardless of whether all or only a portion of the memory cells contain useful data. Therefore, refreshing all memory cells during the refresh mode is not efficient.
For these and other reasons stated below, and which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an efficient method to refresh memory cells in a memory device.
SUMMARY OF THE INVENTION
The present invention includes a memory device having a refresh address selection circuit to store a number of selected rows of memory cells such that during a refresh mode only the memory cells of the selected rows are refreshed.
In one aspect, the memory device includes a counter to count addresses of rows of memory cells, a register to store selected addresses of rows of memory cells, and a compare circuit connected to the counter and the register to compare an address counted by the counter with the selected address such that a row of memory cells located at the address counted by the counter is refreshed if the address counted by the counter is within the selected addresses.
In another aspect, a method of refreshing memory cells of the memory device includes generating a count that represents an address of a row of the memory cells. The address represented by the count is compared with a selected address. Memory cells located at the address represented by the count are refreshed if the address represented by the count matches the selected address.


REFERENCES:
patent: 6215714 (2001-04-01), Takemae et al.
patent: 6349068 (2002-02-01), Takemae et al.
Betty Prince, “Semiconductor Memories”, 1983, Wiley, 2ndedition, pp. 220-221.

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