Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2001-02-07
2003-10-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S105000, C711S166000, C711S167000, C713S001000
Reexamination Certificate
active
06636957
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present disclosure pertains to the field of data processing systems. More particularly, the present disclosure pertains to initializing or configuring memory devices in a memory channel.
2. Description of Related Art
Memory devices and memory subsystems typically have certain initialization steps and/or register values that need to be programmed prior to normal operation. Recommended steps and values are often detailed in a memory specification provided to system designers who design other system hardware interfacing with the memory devices. If initialization routines are further optimized, however, initialization may conclude more quickly, advantageously allowing other system processing to commence sooner.
One channel (i.e., a bus configuration) which requires a significant amount of initialization prior to proper operation is a Rambus™ Direct Rambus Dynamic Random Access Memory Channel (a Direct RDRAM™ Channel). This channel is described in detail in documentation available from Rambus Corporation of Mountain View, Calif. RDRAM memories and memory controllers interfacing with a Rambus channel have various registers that need to be set through the initialization process.
It is clear from Rambus documentation that a number of initialization operations must be performed prior to using a Rambus channel. In general, the memory controller reads all the read-only registers in all RDRAMs, processes this information, and then writes all the read-write registers to place the RDRAMs into the proper operating mode. DeviceID and TRDLY registers are important read-write registers that respectively set the device address for memory transactions and the delay value for memory read data.
A unique serial device identification value may be set for each RDRAM on the channel by looping through the entire serial chain and assigning sequential serial identification numbers (see, e.g., p. 28 of the Direct RDRAM™ 64/72 Mbit Data Sheet). A second ID value simply referred to as a device ID allows memory accesses through the Rambus channel during normal operation. A unique device ID also needs to be set for active devices on the channel; however no specific technique for assigning device IDs is described in the literature.
Additionally, RDRAMs can execute refresh, precharge, current calibration, current sampling, and various other functions (see, e.g., pp. 8-9 of the Direct RDRAM™ 64/72 Mbit Data Sheet). While these commands are generally discussed in the Direct RDRAM™ 64/72 Mbit Data Sheet, a complete initialization sequence may not be provided. Additionally, details of initialization and/or configuration of specific memory controllers may not be available. Thus, the prior art may not provide an adequate or complete method and apparatus for configuring a set of memory devices in a memory channel.
SUMMARY
A method and apparatus for configuring and/or initializing memory devices is disclosed. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
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Rambus, “Direct RMC. d1 data Sheet,” Aug. 7, 1998, pp. 1-104.*
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Nizar Puthiya K.
Stevens William A.
Draeger Jeffrey S.
Intel Corporation
Kim Matthew
Tran Denise
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