Method for forming a field effect transistor having...

Details Method for forming a field effect transistor having... Method for forming a field effect transistor having...

2000-09-28

2003-02-11

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S199000, C438S299000, C438S682000

Reexamination Certificate

active

06518178

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor device fabrication, and more particularly to transistors made using a siliciding process for semiconductor devices that does not significantly reduce the junction breakdown voltages of such devices.
BACKGROUND OF THE INVENTION
Metal oxide silicon field effect transistors (“MOSFETs”) are in common use in integrated circuits performing a variety of functions such as microprocessors, memory devices, etc. A typical MOSFET
10
is illustrated in FIG.
1
. The MOSFET
10
is formed on a substrate
12
of a silicon wafer which has been doped to be of a particular type which, in the example of
FIG. 1
, is p-type. An active portion of the MOSFET
10
is formed between areas
16
,
18
of a field oxide layer of silicon dioxide SiO
2
. The field oxide areas
16
,
18
are typically formed by exposing the silicon wafer
12
to oxygen at an elevated temperature thereby allowing the oxygen to react with the silicon. The field oxide also forms a gate oxide layer
20
.
The substrate
12
on opposite sides of the gate insulator
20
is doped with a type different from the doping of the substrate
12
. In the example of
FIG. 1
, n-type regions
30
,
32
are formed in the p-type substrate
12
. Deeper n-type regions
34
,
36
are also formed in the center of the n-type regions
30
,
32
, respectively, for reasons that will be explained below. The region
30
forms the source of the MOSFET
10
while the region
32
forms the drain of the MOSFET
10
. A gate
40
of the MOSFET
10
is formed on the gate oxide layer
20
by a conductive polysilicon layer.
After the above-described components of the MOSFET
10
have been formed, the substrate
12
is covered with a passivation layer
44
, such as boron phosphorus silicate glass. Vias
48
formed in the passivation layer
44
provide a path for conductors
50
,
52
to extend to the source region
30
and the drain region
32
. Other conductors (not shown in
FIG. 1
) which are also part of a metalization layer extend to the gate
40
and to other MOSFETs and other components on the integrated circuit.
As mentioned above, relatively deep n-type regions
34
,
36
are formed at the center of the source and drain regions
30
,
32
, respectively. The purpose of these deep n-type regions
34
,
36
is to isolate the conductors
50
,
52
from the substrate
12
in the event that the conductors
50
,
52
penetrate too deeply into the source and drain regions
30
,
32
, respectively. However, in
FIG. 1
, the conductors
50
,
52
are shown extending through vias in the passivation layer
44
and terminating at the surface of the substrate
12
. In practice, the conductor
50
,
52
may penetrate a sufficient distance into the regions
30
,
32
to short to the substrate
12
.
In operation, current flows from the drain conductor
52
to the source conductor
50
whenever the voltage applied to the gate
40
is greater than the voltage on the source conductor
50
by the threshold voltage V
T
of the MOSFET
10
. Current flowing from the drain conductor
52
spreads out as it flows through the drain region
32
as illustrated by the arrows in FIG.
1
. Similarly, current converges from several directions as it flows through the source region
30
to the source conductor
50
.
As is well known in the art, the MOSFET structure shown in
FIG. 1
is replete with capacitances. For example, the gate
40
and the substrate
12
form two plates of a capacitor separated by the gate oxide layer
20
, and capacitances are also formed between the gate
40
and the n-type regions
30
,
32
as well as between the n-type regions
30
,
32
and other components. The switching speed of a MOSFET is a function of the time constant of the various components. The time constant is equal to the product of resistance and capacitance. Thus, for example, a higher resistance in the source region
30
results in a longer time for the source-to-drain voltage to reach a desired magnitude. An important factor in this high resistance is the resistance along the surface layer of the n-type regions
30
,
32
as the current flows to or from the conductors
50
,
52
as shown by the arrows, as explained above. If the conductors
50
,
52
could contact the entire surfaces of the n-type regions
30
,
32
, respectively, or the surface resistances of the regions
30
,
32
could be reduced, the switching time constants of the MOSFET
10
could be correspondingly reduced. A faster time constant would allow microprocessors, memory devices, etc., composed of MOSFETs to operate at a higher speed.
One conventional technique for reducing the resistance of MOSFETs is illustrated in
FIG. 2
in which components of the MOSFET
60
that are identical to the MOSFET
10
of
FIG. 1
have been provided with the same reference numeral. The prior art MOSFET
60
uses a siliciding process explained below with reference to FIG.
2
. In the initial process steps, the field oxide areas
16
,
18
, the gate oxide layer
20
, the gate
40
and the n-type regions
30
,
32
,
34
,
36
are formed in the substrate
12
, as illustrated in FIG.
2
A.
The MOSFET
60
differs from the MOSFET
10
of
FIG. 1
by the addition of silicide layers
64
,
66
to the surface of the n-type source and drain regions
30
,
32
, respectively. Basically, siliciding is a process by which a metal silicon compound is formed in the surface of a silicon substrate
12
to reduce the surface resistance of the substrate
12
. Siliciding is typically performed by coating the surface of the substrate
12
with a metal such as titanium, tungsten or molybdenum. The metal is then allowed to react with the silicon to form titanium silicide, tungsten silicide or moly silicide, respectively. Since siliciding consumes a portion of the surface of the silicon, the silicide layers
64
,
66
shown in
FIG. 2B
extend below the original surface of the substrate
12
. As shown in
FIG. 2B
, the silicide layers are masked by the field oxide areas
16
,
18
in a process known as self-aligned siliciding, also known as saliciding. However, the silicide layers
64
,
66
may also be formed using a dedicated mask (not shown).
After the silicide layers
64
,
66
have been added as shown in
FIG. 2B
, the passivation layer
44
and the metal conductors
50
,
52
are added, as shown in FIG.
2
C. As further shown in
FIG. 2C
, the relatively low surface resistance of the silicide layers
64
,
66
allows the current to spread out and flow directly into the drain region
32
and out of the source region
30
. This reduced resistance allows spurious capacitances in the MOSFET
60
to be charged more rapidly. As a result, microprocessors, memory devices, and other semiconductor devices fabricated using a siliciding process as shown in
FIG. 2
can operate at relatively high speeds.
Siliciding is also used to reduce the surface resistance of active areas of bipolar junction transistors
70
, as illustrated in FIG.
3
. As shown in
FIG. 3A
, a bipolar junction transistor
70
is fabricated by first forming a field oxide layer on a silicon substrate
72
at areas
74
,
76
,
78
. As shown in
FIG. 3A
, the substrate
72
is doped with p-type material to form a p-type substrate
72
. Next, as shown in
FIG. 3B
, the exposed areas of the substrate
72
between the field oxide areas
74
-
78
are doped to form an n-type collector
80
and an n-type emitter
82
. As with the MOSFET
60
shown in
FIG. 2
, relatively deep n-type regions
84
,
86
are also formed to prevent conductors from shorting to the substrate
72
, as explained below. The n-type regions
80
,
82
and the p-type substrate
72
form an N-P-N transistor as shown schematically at
88
.
In the next step, silicide layers
90
,
92
are formed on the exposed surfaces of the collector and emitter regions
80
,
82
, respectively. As with the MOSFET
60
of
FIG. 2
, the silicide layers
90
,
92
are applied using the field oxide areas
74
,
76
,
78
as a mask in a saliciding process. However, a dedicated mask may also be used. After

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