Method of forming a silicon controlled rectifier devices in...

Details Method of forming a silicon controlled rectifier devices in... Method of forming a silicon controlled rectifier devices in...

2001-10-22

2003-02-18

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S141000, C257S162000, C257S173000

Reexamination Certificate

active

06521952

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates in general to electrostatic discharge (ESD) protection for integrated circuits, and especially to silicon controlled rectifier (SCR) structures fabricated in SOI technology for providing electrostatic discharge protection to integrated circuits.
2. Description of the Prior Art
Recent advances in integrated circuits have included the further development of silicon-on-insulator (SOI) technology, in which an insulator layer is embedded within a substrate and extends beneath the active regions of an integrated circuit. There are many advantages in SOI devices, including nearly perfect sub-threshold swing, latch-up free operation, low off-state leakage, low operating voltage, and high current driving ability. But, electrostatic discharge (ESD) presents an issue due to bad thermal conductivity of the buried oxide and its floating body effect.
ESD often causes damage to semiconductor devices on an integrated circuit during handling of the IC package. An electrostatic discharge often has an extremely high voltage that easily destroys the thin gate oxide of devices in CMOS IC's. To prevent such ESD damage, the on-chip ESD protection circuits are typically incorporated into the chip of the integrated circuit. In general, such protection circuits include a switch that can be turned on and that is capable of conducting relatively large currents during an ESD event, but which stays turned off when the IC is under normal operating conditions. SCR devices typically have low holding voltages (V
hold
~1V) in bulk (non-epitaxial) CMOS processes.
The power dissipation (power≈I
esd
*V
hold
) of the SCR device during ESD-related stress is thus less than that for other ESD protection devices (such as diodes, MOS's, BJT's or field-oxide devices) in CMOS technology. Therefore, SCR devices can sustain a much higher ESD level within a smaller layout area in CMOS IC's, and have been used as the main ESD clamping devices in ESD protection circuitry.
Since SCR devices have a switching voltage that exceeds 30 volts in sub-micron CMOS processes, they are not suitable for protecting the gate oxides in sub-micron CMOS technology, which typically have a breakdown voltage of less than 20 volts. Additional secondary protection circuits are often added into an on-chip ESD protection circuit that uses a SCR device to provide the overall ESD protection functionality for the IC. In order to improve the protection efficiency of SCR devices, several modified designs have been disclosed that use SCR devices in on-chip ESD protection circuitry.
In U.S. Pat. No. 5,012,317, a SCR device realized in a P-substrate/N-well CMOS process is proposed. Please refer to FIG.
1
.
FIG. 1
is a cross-sectional schematic diagram of a SCR device
10
realized in a P-substrate/N-well CMOS process according to the prior art. As shown in
FIG. 1
, the SCR device
10
is made in a silicon substrate. The silicon substrate comprises a P-type substrate
11
and an N well
12
in the P-type substrate
11
, a P
+
region
14
in the N well
12
for use as an anode of the SCR device
10
(the input terminal of the SCR device
10
), and an N
+
region
15
in the P-type substrate
11
for use as a cathode of the SCR device
10
(the ground terminal of the SCR device
10
). The P
+
region
14
, the N well
12
, the P-type substrate
11
and the N
+
region
15
form the SCR device
10
. Such a SCR device is triggered on by the junction breakdown across the P-type substrate/N well junction. When the SCR device
10
is triggered on, ESD current flows from the P
+
region
14
, through the N well
12
, through the P-type substrate
11
, through the N
+
region
15
, and then to ground for discharging. As described above, such a SCR device often has a high switching voltage (greater than 30V in a 0.35 &mgr;m CMOS process). With a higher switching voltage, the SCR device
10
needs an additional secondary protection circuit to provide the overall ESD protection functionality to the IC.
In U.S. Pat. No. 5,225,702, a modified design for a SCR device is proposed. Please refer to FIG.
2
.
FIG. 2
is a cross-sectional schematic diagram of a modified design of a SCR device
20
according to the prior art. As shown in
FIG. 2
, the modified SCR device
20
is made on a silicon substrate. The silicon substrate comprises a P-type substrate
21
with an N well
22
in the P-type substrate
21
, a P
+
region
24
in the N well
22
for electrically connecting to the anode, which is normally the input terminal, an N
+
region
25
in the P-type substrate
21
for electrically connecting to the cathode, which is normally the ground terminal, and an N
+
diffusion region
26
that is added across the P-type substrate/N well junction. The P
+
region
24
, the N well
22
, the P-type substrate
21
, the N
+
region
25
, and the additional N
+
diffusion region
26
together form the modified SCR device
20
. With the inserted N
+
diffusion region
26
, the switching voltage of this SCR
20
is reduced to the breakdown voltage across the N
+
diffusion region/P-type substrate junction. Such a modified SCR device
20
typically has a switching voltage of about 12V for a 0.35 &mgr;m CMOS process. With a lower switching voltage, the SCR device
20
can be triggered on more quickly to discharge ESD current.
In U.S. Pat. No. 5,453,384, another modification of a SCR device is proposed, with an NMOS device added across the P-type substrate/N well junction. Please refer to FIG.
3
.
FIG. 3
is a cross-sectional schematic diagram of a second modified design of a SCR device
30
according to the prior art. As shown in
FIG. 3
, the SCR device
30
is made on a silicon substrate. The silicon substrate comprises a P-type substrate
31
with an N well
32
in the P-type substrate
31
, a P
+
region
34
in the N well
32
for electrically connecting to the anode, which is normally the input terminal, an N
+
region
35
in the P-type substrate
31
for electrically connecting to the cathode, which is normally the ground terminal, and an N
+
diffusion region
36
across the N well
32
and the P-type substrate
31
. The P
+
region
34
, the N well
32
, the P-type substrate
31
, and the N
+
region
35
form the second modified design of the SCR device
30
.
Compared to the previously described design for the SCR device
20
, the SCR device
30
further comprises a gate insulator
37
together with a gate
38
, which are formed between the N
+
diffusion region
36
and the N
+
region
35
. Both a spacer
39
and a lightly doped drain
40
(in the P-type substrate
31
) are formed on either side of the gate
38
. An additional NMOS device
42
is thereby formed. In
FIG. 3
, shallow-trench-isolation (STI) regions
44
are also indicated in the structure of the SCR device
30
to indicate that such a SCR device
30
is formed using deep-submicron CMOS processes. With the additional NMOS device
42
, the switching voltage of the SCR device
30
is reduced to the drain breakdown voltage of the inserted NMOS device
42
across the P-type substrate/N well junction. The SCR device
30
typically has a switching voltage of about 8V in 0.35 &mgr;m CMOS processes. With a sufficiently lowered switching voltage, the SCR device
30
can protect an IC in a standalone configuration without the need for extra secondary protection circuits.
Continuous advances in silicon-on-insulator (SOI) techniques are being made, which brings eminent progress to IC process. The SOI technique involves the formation of an insulator layer (a buried oxide layer) in the substrate, which extends beneath the active doping region of the integrated circuit. SOI devices have many advantages, such as nearly perfect sub-threshold swing, latch-up free operation, a low off-state leakage, a low operating voltage, and high current driving capabilities. However, due to the poor thermal conductivity of the buri

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