Method of forming semiconductor devices with differently...

Details Method of forming semiconductor devices with differently... Method of forming semiconductor devices with differently...

2001-03-21

2003-02-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S224000, C438S228000, C438S592000

Reexamination Certificate

active

06518154

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of manufacturing semiconductor devices including a plurality of active device regions each having a gate electrode, e.g., CMOS devices comprised of one or more of each of NMOS and PMOS transistors. More specifically, the present invention relates to methods of manufacturing CMOS devices wherein the gate electrodes of the various transistors are formed of different metal-based, electrically conductive materials, and to the devices thereby produced. The present invention has particular utility in the manufacture of high integration density semiconductor devices employing design rules of 0.20 &mgr;m and below, e.g., 0.15 &mgr;m and below.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance (e.g., transistor and circuit speeds) associated with ultra-large scale integration (“ULSI”) devices necessitate design rules for component features of 0.20 &mgr;m and below, e.g., 0.15 &mgr;m and below, such as source, drain, and gate regions and electrodes therefor formed in or on a common semiconductor substrate, challenges the limitations of conventional materials and manufacturing processes and necessitates use of alternative materials and development of new methodologies therefor.
An example of the above-mentioned challenge based upon the limitations inherent in conventional materials and methodologies utilized in the semiconductor integrated circuit (“IC”) industry is the use of polysilicon for forming gate electrodes of metal-oxide-semiconductor (“MOS”) transistors. Polysilicon is conventionally employed as a gate electrode material in MOS transistors in view of its good thermal stability, i.e., ability to withstand high temperature processing. More specifically, the good thermal stability of polysilicon-based materials permits high temperature annealing thereof during formation/activation of implanted source and drain regions. In addition, polysilicon-based materials advantageously block implantation of dopant ions into the underlying channel region of the transistor, thereby facilitating formation of self-aligned source and drain regions after gate electrode deposition/patterning is completed.
However, polysilicon-based gate electrodes incur a number of disadvantages, including, inter alia: (1) as device design rules decrease to below about 0.20 &mgr;m, polysilicon gates are adversely affected by poly depletion, wherein the effective gate oxide thickness (“EOT”) is increased. Such increase in EOT can reduce performance by about 15% or more; (2) polysilicon-based gate electrodes have higher resistivities than most metal or metallic materials and thus devices including polysilicon as electrode or circuit materials operate at a much slower speed than equivalent devices utilizing metal-based materials. Further, a significant portion of the voltage applied to the gate during operation is dropped in the polysilicon due to the poor conductivity of silicon. As a consequence, in order to compensate for the higher resistance, polysilicon-based materials require suicide processing in order to decrease their resistance and thus increase the operational speeds of polysilicon-based devices to acceptable levels; (3) use of polysilicon-based gates necessitates ion implantation of different dopant atoms for p-channel transistors and n-channel transistors formed in a CMOS device, which different dopant species are required for the p-channel and n-channel transistors to have compatible threshold voltages (“V
t
,”). Disadvantageously, the threshold adjust implant is of sufficiently high doping concentration as to adversely impact the mobility of charge carriers in and through the channel region; and (4) polysilicon-based gate electrodes are less compatible with high dielectric constant (“high-k”) materials (i.e., >5, preferably >20) which are desirable for use as gate oxide layers, than are metal-based gate electrodes.
In view of the above-described drawbacks and disadvantages associated with the use of polysilicon-based materials as gate electrodes in MOS and CMOS transistor devices, several process schemes have been proposed for making self-aligned MOS and/or CMOS transistor devices utilizing metal-based gate electrode materials.
Metal or metal-based gate electrode materials for use in MOS and/or CMOS devices offer a number of advantages vis-à-vis conventional polysilicon-based materials, including: (1) since many metal materials are mid-gap work function materials, the same metal gate material can, under favorable circumstances, function as a gate electrode for both n-channel and p-channel transistors in a CMOS process without disadvantageously requiring threshold voltage (V
t
) adjust implants, while maintaining V
t
at compatible levels; (2) metal gate electrodes have a greater conductivity than polysilicon electrodes; (3) unlike polysilicon-based gate electrodes, metal gate electrodes do not suffer from polysilicon depletion which alters the EOT of an MOS transistor, thereby affecting the performance of the MOS device (i.e., thinner EOTs, while possibly resulting in an increased leakage current, result in faster operating devices); (4) metal gate MOS devices are advantageous for use in fully-depleted silicon-on-insulator (“SOI”) devices since V
t
of these devices can be more accurately controlled; and (5) metal gate electrodes are more compatible with high-k dielectrics than conventional polysilicon processing.
The use of metal or metallic materials as replacements for polysilicon-based materials as gate electrodes in MOS and/or CMOS devices incurs several difficulties, however, which difficulties must be considered and overcome in any metal-based gate electrode process scheme, including: (1) metal and/or metal-based gates cannot withstand the higher temperatures and oxidative ambients which conventional polysilicon-based gate electrode materials are capable of withstanding; (2) several candidate metals or metallic materials for use as gate electrodes do not exhibit adequate adhesion in film form to surrounding layers of different materials when these metals or metallic materials are patterned to very small geometries; (3) some metal or metallic films are difficult to lithographically pattern and etch via conventional processing techniques because etching thereof may significantly damage underlying oxides, thereby adversely affecting device performance; (4) thermal processing subsequent to metal gate electrode formation may result in instability and degradation of the gate oxide due to chemical interaction between the metal and oxide at the metal gate-gate oxide interface; and (5) high thermal expansion coefficients of metals with respect to silicon can lead to undesirably high stress levels.
A conventional process scheme for forming silicon-based MOS transistors of different channel conductivity type (i.e., NMOS and PMOS transistors) in or on a common semiconductor substrate, as in CMOS devices, is schematically illustrated in FIGS.
1
(A)-
1
(H). As shown in FIG.
1
(A), a preliminary structure
10
is provided which comprises at least one field oxide region
115
or other type conventional isolation means (such as shallow trench isolation (“STI”)) formed in semiconductor substrate
100
, typically of monocrystalline Si, to electrically separate p-type well regions
101
and n-type well regions
102
(referred to hereinafter as active device or transistor “precursor regions”) formed therein, e.g., by conventional dopant diffusion or implantation. Preliminary structure
10
further includes a thin gate insulator layer
105
, typically a silicon oxide layer, formed in contact with the upper surface of substrate
100
, as by thermal oxidation.
Referring now to FIG.
1
(B), a layer
110
of an electrically conductive gate electrode material, typically of heavily-doped polysilicon, is formed over the thin gate insulator layer
105
and patterned, as by conventional photolithographic masking and etching techniques, to form a pair of layer stacks
105
/
110
overlying respective portions of the s

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