Modified charge recycling differential logic

Details Modified charge recycling differential logic Modified charge recycling differential logic

2001-12-20

2003-10-07

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S121000, C365S205000

Reexamination Certificate

active

06630846

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to charge recycling differential logic circuits.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power and space efficient alternatives. As part of this effort, charge recycling differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1A
shows a prior art charge recycling differential logic circuit
100
A and associated prior art control circuit
100
B. As seen in
FIG. 1A
, prior art charge recycling differential logic circuit
100
A required six transistors: PFET
105
, PFET
107
, NFET
109
, NFET
115
, NFET
117
and NFET
121
. Prior art charge recycling differential logic circuit
100
A also included differential logic
123
with control variable inputs
151
and
153
, pass variable inputs
155
and
157
, output
111
and outBar
113
. In addition, PFET
105
and PFET
107
of prior art charge recycling differential logic circuit
100
A included back biasing inputs
131
and
133
having a voltage Vbb applied.
As discussed below, prior art charge recycling differential logic circuit
100
A also required control circuit
100
B. Control circuit
100
B included three additional transistors: PFET
137
; PFET
135
; and NFET
139
. Prior art control circuit
100
B also included an enable out signal (eout) at terminal
143
. According to the prior art, the control signal eout, at terminal
143
was supplied to a prior art charge recycling differential logic circuit
100
A as control signal ein at terminal
119
as discussed below.
In
FIG. 1A
, prior art charge recycling differential logic circuit
100
A and associated prior art control circuit
100
B are shown separately for simplicity and clarity. However, in practice prior art charge recycling differential logic circuit
100
A and associated prior art control circuit
100
B are combined in a single circuit.
FIG. 1B
shows one combination of prior art charge recycling differential logic circuit
100
A and associated prior art control circuit
100
B into the resulting prior art charge recycling differential logic circuit
100
C. As shown in
FIG. 1B
, prior art charge recycling differential logic circuit
100
C required nine transistors: PFET
105
, PFET
107
, NFET
109
, NFET
115
, NFET
117
, NFET
121
, PFET
137
; PFET
135
; and NFET
139
. Prior art charge recycling differential logic circuit
100
C also included differential logic
123
with control variable inputs
151
and
153
, pass variable inputs
155
and
157
, output
111
and outBar
113
. In addition, PFET
105
and PFET
107
of prior art charge recycling differential logic circuit
100
C included back biasing inputs
131
and
133
having a voltage Vbb applied. Prior art charge recycling differential logic circuit
100
C also included an enable out signal (eout) at terminal
143
. According to the prior art, the control signal eout, at terminal
143
was supplied to a following prior art charge recycling differential logic circuit (not shown) as control signal ein at a corresponding input terminal as discussed below.
As discussed above, prior art charge recycling differential logic circuit
100
C required an enable in (ein) signal, coupled to the gate of NFET
121
. The control signal ein was supplied by a prior art control circuit, similar to prior art control circuit
100
B in
FIG. 1A
, of the previous stage. When multiple prior art charge recycling differential logic circuits
100
C were cascaded together, prior art control circuit
100
B and control signal ein was necessitated to ensure that each prior art charge recycling differential logic circuit
100
C switched or “fired” only after it had received an input from the previous stage.
As noted above, when multiple prior art charge recycling differential logic circuits
100
C were cascaded together, each prior art charge recycling differential logic circuit
100
C required prior art control circuit
100
B to ensure that each prior art charge recycling differential logic circuit
100
C switched or “fired” only after it had received an input from the previous stage. However, prior art control circuit
100
B added significant complexity to prior art charge recycling differential logic circuit
100
C, requiring at least three additional transistors and several circuit lines. Consequently, prior art charge recycling differential logic circuit
100
C required significant additional components and space. This, in turn, meant that prior art charge recycling differential logic circuit
100
C required more silicon, a more complex design, more components to potentially fail and more components to produce heat.
In addition, prior art control circuit
100
B not only added complexity to prior art charge recycling differential logic circuits
100
C, but it also loaded the output nodes
111
and
113
of prior art charge recycling differential logic circuit
100
C and drew current from output nodes
111
and
113
of prior art charge recycling differential logic circuit
100
C to charge the control signal ein. In addition, in the prior art, if prior art control circuit
100
B were made small, the control signal ein was slow, and this slowed down the operation of prior art charge recycling differential logic circuit
100
C. Consequently, there was pressure to increase the size of prior art control circuit
100
B. However, Increasing the size of prior art control circuit
100
B to speed up the control signal ein also increased the loading on the output nodes
111
and
113
of prior art charge recycling differential logic circuit
100
C and therefore slowed down the evaluation of logic
123
.
What is needed is a method and apparatus for creating charge recycling differential logic that does not require the complex control circuitry of prior art charge recycling differential logic circuits and is therefore simpler, more space efficient and is more reliable than prior art charge recycling differential logic circuits.
SUMMARY OF THE INVENTION
According to the invention, the prior art control circuitry is eliminated. The clocked charge recycling differential logic circuit of the invention is instead activated from a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit of the invention. Each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit.
According to the invention, clocked charge recycling differential logic circuits do not require the significant additional components used in the prior art. This, in turn, means that the clocked charge recycling differential logic circuits of the invention require less space, are simpler, dissipate less heat and have fewer components to potentially fail. In addition, clocked charge recycling differential logic circuits of the invention eliminate the loading of the output nodes of the charge recycling differential logic circuit since there is no control signal ein, and therefore no prior art control circuits to draw current from the output nodes to charge the control signal ein. Consequently, using the clocked charge recycling differential logic circuits of the invention, speed is increased because there is less loading on the output nodes and the clocked charge recycling differential logic circuit of the invention can start evaluating

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