Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate
2001-11-27
2003-10-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
With shift register
C365S078000, C365S230080, C365S230090, C365S239000, C365S240000, C714S727000
Reexamination Certificate
active
06639850
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-304750, filed Sep. 28, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a latching means capable of scanning.
2. Description of the Related Art
In synchronous semiconductor integrated circuits which have been more and more complicated, the recent most popular technique is to use a latching circuit (scan chain) capable of scanning to test this latching circuit by separating only a certain function, thereby greatly reducing the test time. The latching means (scan chain) capable of scanning is a means in which a plurality of registers and the like are connected into one or a plurality of chains so that data stored in a preceding register can be shifted (scanned) to a succeeding register.
In particular, a macro cell for forming an embedded memory containing both a memory circuit and logic circuit has a large number of input/output terminals. Hence, it is essential to include the scanning function as described above to improve the fault detection ratio of the whole semiconductor integrated circuit (semiconductor chip).
FIG. 1
is a schematic view showing a method of realizing scan in a conventional macro cell. This macro cell
101
is for forming an embedded memory or the like. As shown in
FIG. 1
, the macro cell
101
has a large number of input/output terminals (to be referred to as IO terminals hereinafter)
102
, so these IO terminals
102
are arranged with a spatial extension. Each IO terminal
102
has an input/output register (to be referred to as an IO register hereinafter)
103
. These IO registers
103
have a scanning function to test data (an external path) input from the outside of this macro cell, and are connected in series.
A scan input terminal
104
is connected to one end of these IO registers
103
. A scan output terminal
105
is connected to the other end of the IO registers
103
. Data SI to be scanned is input to the input terminal
104
, and scanned data SO is output from the scan output terminal
105
. Although not shown, scan is executed by using a control input signal and a clock signal in addition to these data.
FIG. 2
is a view showing the arrangement of a conventional embedded memory macro. An example of the realization of scan in this embedded memory macro will be described below.
As shown in
FIG. 2
, this embedded memory macro
111
has the macro cell
101
shown in
FIG. 1
, an operation control circuit
112
, and a macro cell
101
B. This macro cell
101
B is the mirror inversion of the macro cell
101
with respect to the operation control circuit
112
. In an embedded memory macro, to increase the memory capacity and share the operation control circuit
112
, the macro cells
101
and
101
B are usually so arranged as to have a mirror inversion relationship on the two sides of the operation control circuit
112
.
In each of the macro cells
101
and
101
B, 128 IO registers and 128 IO terminals are arranged. At the right end of the macro cell
101
, a scan input terminal
104
connected to the right end of the IO registers is formed. At the left end of the macro cell
101
, a scan output terminal
105
connected to the left end of the IO registers is formed.
The operation control circuit
112
has an input/output line for inputting and outputting a control signal CNT and has a register for storing this control signal CNT. At the right end of the operation control circuit
112
, a scan input terminal
113
connected to the register is formed. At the lower end of the operation control circuit
112
, a scan output terminal
114
connected to the register is formed.
At the left end of the macro cell
101
B, a scan input terminal
104
B connected to the left end of the IO registers is formed. At the right end of the macro cell
101
B, a scan output terminal
105
B connected to the right end of the IO registers is formed. In addition, the scan output terminal
114
and the scan input terminal
104
B are connected by a line
115
.
The memory macro
111
configured as shown in
FIG. 2
can achieve a memory macro scanning function by inputting data SI to be scanned to the scan input terminal
104
at the right end, and outputting scanned data SO from the scan output terminal
105
B.
Unfortunately, the line
115
between the scan output terminal
114
and the scan input terminal
104
B is a long line extending over the 128 IO terminals, and therefore deteriorates the performance of the scan operation. Also, this line
115
must be formed outside the memory macro. This interferes with automatization of the scan operation.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention comprises: circuits having a certain function; a plurality of input terminals which receive input data to the circuits from the outside; a plurality of output terminals which output data output from the circuits to the outside; a plurality of first registers connected in series, the plurality of first registers shifting stored data to respective adjacent registers in sequence, and the plurality of first registers being connected in one-to-one correspondence to the plurality of input terminals or to the plurality of output terminals; a plurality of second registers connected in series, the plurality of second registers shifting stored data to respective adjacent registers in sequence, and the plurality of second registers being connected in one-to-one correspondence to the plurality of input terminals or to the plurality of output terminals; a first scan input terminal formed at one end of the plurality of first series-connected registers; a first scan output terminal formed at the other end of the plurality of first series-connected registers; a second scan input terminal formed at one end of the plurality of second series-connected registers; a second scan output terminal formed at the other end of the plurality of second series-connected registers; and an operation control circuit which controls operations of the circuits and the plurality of first and second registers.
REFERENCES:
patent: 6154396 (2000-11-01), Yabe et al.
patent: 6408414 (2002-06-01), Hatada
patent: 6445627 (2002-09-01), Nakahara et al.
patent: 2001/0047499 (2001-11-01), Whetsel, Jr.
patent: 2002/0120895 (2002-08-01), Suzuki
Jun Ohtani, et al. “A Shared Built-In Self-Repair Analysis for Multiple Embedded Memories,” IEEE 2001 Custom Integrated Circuits Conference. 2001, pp. 187-190.
Elms Richard
Kabushiki Kaisha Toshiba
Le Toan
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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